--- /dev/null
+/** @file\r
+ NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
+ NVM Express specification.\r
+\r
+ Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _NVME_HCI_H_\r
+#define _NVME_HCI_H_\r
+\r
+#define NVME_BAR 0\r
+\r
+//\r
+// controller register offsets\r
+//\r
+#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
+#define NVME_VER_OFFSET 0x0008 // Version\r
+#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
+#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
+#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
+#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
+#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
+#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
+#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
+#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
+#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
+\r
+//\r
+// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
+// Get the doorbell stride bit shift value from the controller capabilities.\r
+//\r
+#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
+#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
+\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
+//\r
+typedef struct {\r
+ UINT16 Mqes; // Maximum Queue Entries Supported\r
+ UINT8 Cqr:1; // Contiguous Queues Required\r
+ UINT8 Ams:2; // Arbitration Mechanism Supported\r
+ UINT8 Rsvd1:5;\r
+ UINT8 To; // Timeout\r
+ UINT16 Dstrd:4;\r
+ UINT16 Rsvd2:1;\r
+ UINT16 Css:4; // Command Sets Supported\r
+ UINT16 Rsvd3:7;\r
+ UINT8 Mpsmin:4;\r
+ UINT8 Mpsmax:4;\r
+ UINT8 Rsvd4;\r
+} NVME_CAP;\r
+\r
+//\r
+// 3.1.2 Offset 08h: VS - Version\r
+//\r
+typedef struct {\r
+ UINT16 Mnr; // Minor version number\r
+ UINT16 Mjr; // Major version number\r
+} NVME_VER;\r
+\r
+//\r
+// 3.1.5 Offset 14h: CC - Controller Configuration\r
+//\r
+typedef struct {\r
+ UINT16 En:1; // Enable\r
+ UINT16 Rsvd1:3;\r
+ UINT16 Css:3; // Command Set Selected\r
+ UINT16 Mps:4; // Memory Page Size\r
+ UINT16 Ams:3; // Arbitration Mechanism Selected\r
+ UINT16 Shn:2; // Shutdown Notification\r
+ UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
+ UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
+ UINT8 Rsvd2;\r
+} NVME_CC;\r
+\r
+//\r
+// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
+//\r
+typedef struct {\r
+ UINT32 Rdy:1; // Ready\r
+ UINT32 Cfs:1; // Controller Fatal Status\r
+ UINT32 Shst:2; // Shutdown Status\r
+ UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
+ UINT32 Rsvd1:27;\r
+} NVME_CSTS;\r
+\r
+//\r
+// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
+//\r
+typedef struct {\r
+ UINT16 Asqs:12; // Submission Queue Size\r
+ UINT16 Rsvd1:4;\r
+ UINT16 Acqs:12; // Completion Queue Size\r
+ UINT16 Rsvd2:4;\r
+} NVME_AQA;\r
+\r
+//\r
+// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
+//\r
+typedef struct {\r
+ UINT64 Rsvd1:12;\r
+ UINT64 Asqb:52; // Admin Submission Queue Base Address\r
+} NVME_ASQ;\r
+\r
+//\r
+// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
+//\r
+typedef struct {\r
+ UINT64 Rsvd1:12;\r
+ UINT64 Acqb:52; // Admin Completion Queue Base Address\r
+} NVME_ACQ;\r
+\r
+//\r
+// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
+//\r
+typedef struct {\r
+ UINT16 Sqt;\r
+ UINT16 Rsvd1;\r
+} NVME_SQTDBL;\r
+\r
+//\r
+// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
+//\r
+typedef struct {\r
+ UINT16 Cqh;\r
+ UINT16 Rsvd1;\r
+} NVME_CQHDBL;\r
+\r
+//\r
+// NVM command set structures\r
+//\r
+// Read Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10, 11\r
+ //\r
+ UINT64 Slba; /* Starting Sector Address */\r
+ //\r
+ // CDW 12\r
+ //\r
+ UINT16 Nlb; /* Number of Sectors */\r
+ UINT16 Rsvd1:10;\r
+ UINT16 Prinfo:4; /* Protection Info Check */\r
+ UINT16 Fua:1; /* Force Unit Access */\r
+ UINT16 Lr:1; /* Limited Retry */\r
+ //\r
+ // CDW 13\r
+ //\r
+ UINT32 Af:4; /* Access Frequency */\r
+ UINT32 Al:2; /* Access Latency */\r
+ UINT32 Sr:1; /* Sequential Request */\r
+ UINT32 In:1; /* Incompressible */\r
+ UINT32 Rsvd2:24;\r
+ //\r
+ // CDW 14\r
+ //\r
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
+ //\r
+ // CDW 15\r
+ //\r
+ UINT16 Elbat; /* Expected Logical Block Application Tag */\r
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
+} NVME_READ;\r
+\r
+//\r
+// Write Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10, 11\r
+ //\r
+ UINT64 Slba; /* Starting Sector Address */\r
+ //\r
+ // CDW 12\r
+ //\r
+ UINT16 Nlb; /* Number of Sectors */\r
+ UINT16 Rsvd1:10;\r
+ UINT16 Prinfo:4; /* Protection Info Check */\r
+ UINT16 Fua:1; /* Force Unit Access */\r
+ UINT16 Lr:1; /* Limited Retry */\r
+ //\r
+ // CDW 13\r
+ //\r
+ UINT32 Af:4; /* Access Frequency */\r
+ UINT32 Al:2; /* Access Latency */\r
+ UINT32 Sr:1; /* Sequential Request */\r
+ UINT32 In:1; /* Incompressible */\r
+ UINT32 Rsvd2:24;\r
+ //\r
+ // CDW 14\r
+ //\r
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
+ //\r
+ // CDW 15\r
+ //\r
+ UINT16 Lbat; /* Logical Block Application Tag */\r
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
+} NVME_WRITE;\r
+\r
+//\r
+// Flush\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Flush; /* Flush */\r
+} NVME_FLUSH;\r
+\r
+//\r
+// Write Uncorrectable command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10, 11\r
+ //\r
+ UINT64 Slba; /* Starting LBA */\r
+ //\r
+ // CDW 12\r
+ //\r
+ UINT32 Nlb:16; /* Number of Logical Blocks */\r
+ UINT32 Rsvd1:16;\r
+} NVME_WRITE_UNCORRECTABLE;\r
+\r
+//\r
+// Write Zeroes command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10, 11\r
+ //\r
+ UINT64 Slba; /* Starting LBA */\r
+ //\r
+ // CDW 12\r
+ //\r
+ UINT16 Nlb; /* Number of Logical Blocks */\r
+ UINT16 Rsvd1:10;\r
+ UINT16 Prinfo:4; /* Protection Info Check */\r
+ UINT16 Fua:1; /* Force Unit Access */\r
+ UINT16 Lr:1; /* Limited Retry */\r
+ //\r
+ // CDW 13\r
+ //\r
+ UINT32 Rsvd2;\r
+ //\r
+ // CDW 14\r
+ //\r
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
+ //\r
+ // CDW 15\r
+ //\r
+ UINT16 Lbat; /* Logical Block Application Tag */\r
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
+} NVME_WRITE_ZEROES;\r
+\r
+//\r
+// Compare command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10, 11\r
+ //\r
+ UINT64 Slba; /* Starting LBA */\r
+ //\r
+ // CDW 12\r
+ //\r
+ UINT16 Nlb; /* Number of Logical Blocks */\r
+ UINT16 Rsvd1:10;\r
+ UINT16 Prinfo:4; /* Protection Info Check */\r
+ UINT16 Fua:1; /* Force Unit Access */\r
+ UINT16 Lr:1; /* Limited Retry */\r
+ //\r
+ // CDW 13\r
+ //\r
+ UINT32 Rsvd2;\r
+ //\r
+ // CDW 14\r
+ //\r
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
+ //\r
+ // CDW 15\r
+ //\r
+ UINT16 Elbat; /* Expected Logical Block Application Tag */\r
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
+} NVME_COMPARE;\r
+\r
+typedef union {\r
+ NVME_READ Read;\r
+ NVME_WRITE Write;\r
+ NVME_FLUSH Flush;\r
+ NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r
+ NVME_WRITE_ZEROES WriteZeros;\r
+ NVME_COMPARE Compare;\r
+} NVME_CMD;\r
+\r
+typedef struct {\r
+ UINT16 Mp; /* Maximum Power */\r
+ UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Mps:1; /* Max Power Scale */\r
+ UINT8 Nops:1; /* Non-Operational State */\r
+ UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Enlat; /* Entry Latency */\r
+ UINT32 Exlat; /* Exit Latency */\r
+ UINT8 Rrt:5; /* Relative Read Throughput */\r
+ UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rrl:5; /* Relative Read Leatency */\r
+ UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rwt:5; /* Relative Write Throughput */\r
+ UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rwl:5; /* Relative Write Leatency */\r
+ UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
+} NVME_PSDESCRIPTOR;\r
+\r
+//\r
+// Identify Controller Data\r
+//\r
+typedef struct {\r
+ //\r
+ // Controller Capabilities and Features 0-255\r
+ //\r
+ UINT16 Vid; /* PCI Vendor ID */\r
+ UINT16 Ssvid; /* PCI sub-system vendor ID */\r
+ UINT8 Sn[20]; /* Produce serial number */\r
+\r
+ UINT8 Mn[40]; /* Proeduct model number */\r
+ UINT8 Fr[8]; /* Firmware Revision */\r
+ UINT8 Rab; /* Recommended Arbitration Burst */\r
+ UINT8 Ieee_oiu[3]; /* Organization Unique Identifier */\r
+ UINT8 Cmic; /* Multi-interface Capabilities */\r
+ UINT8 Mdts; /* Maximum Data Transfer Size */\r
+ UINT8 Cntlid[2]; /* Controller ID */\r
+ UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ //\r
+ // Admin Command Set Attributes\r
+ //\r
+ UINT16 Oacs; /* Optional Admin Command Support */\r
+ UINT8 Acl; /* Abort Command Limit */\r
+ UINT8 Aerl; /* Async Event Request Limit */\r
+ UINT8 Frmw; /* Firmware updates */\r
+ UINT8 Lpa; /* Log Page Attributes */\r
+ UINT8 Elpe; /* Error Log Page Entries */\r
+ UINT8 Npss; /* Number of Power States Support */\r
+ UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
+ UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
+ UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ //\r
+ // NVM Command Set Attributes\r
+ //\r
+ UINT8 Sqes; /* Submission Queue Entry Size */\r
+ UINT8 Cqes; /* Completion Queue Entry Size */\r
+ UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Nn; /* Number of Namespaces */\r
+ UINT16 Oncs; /* Optional NVM Command Support */\r
+ UINT16 Fuses; /* Fused Operation Support */\r
+ UINT8 Fna; /* Format NVM Attributes */\r
+ UINT8 Vwc; /* Volatile Write Cache */\r
+ UINT16 Awun; /* Atomic Write Unit Normal */\r
+ UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
+ UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
+ UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT16 Acwu; /* Atomic Compare & Write Unit */\r
+ UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Sgls; /* SGL Support */\r
+ UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ //\r
+ // I/O Command set Attributes\r
+ //\r
+ UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ //\r
+ // Power State Descriptors\r
+ //\r
+ NVME_PSDESCRIPTOR PsDescriptor[32];\r
+\r
+ UINT8 VendorData[1024]; /* Vendor specific data */\r
+} NVME_ADMIN_CONTROLLER_DATA;\r
+\r
+typedef struct {\r
+ UINT16 Ms; /* Metadata Size */\r
+ UINT8 Lbads; /* LBA Data Size */\r
+ UINT8 Rp:2; /* Relative Performance */\r
+ #define LBAF_RP_BEST 00b\r
+ #define LBAF_RP_BETTER 01b\r
+ #define LBAF_RP_GOOD 10b\r
+ #define LBAF_RP_DEGRADED 11b\r
+ UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
+} NVME_LBAFORMAT;\r
+\r
+//\r
+// Identify Namespace Data\r
+//\r
+typedef struct {\r
+ //\r
+ // NVM Command Set Specific\r
+ //\r
+ UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
+ UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
+ UINT64 Nuse; /* Namespace Utilization */\r
+ UINT8 Nsfeat; /* Namespace Features */\r
+ UINT8 Nlbaf; /* Number of LBA Formats */\r
+ UINT8 Flbas; /* Formatted LBA size */\r
+ UINT8 Mc; /* Metadata Capabilities */\r
+ UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
+ UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
+ UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
+ UINT8 Rescap; /* Reservation Capabilities */\r
+ UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
+ //\r
+ // LBA Format\r
+ //\r
+ NVME_LBAFORMAT LbaFormat[16];\r
+\r
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 VendorData[3712]; /* Vendor specific data */\r
+} NVME_ADMIN_NAMESPACE_DATA;\r
+\r
+//\r
+// NvmExpress Admin Identify Cmd\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Cns:2;\r
+ UINT32 Rsvd1:30;\r
+} NVME_ADMIN_IDENTIFY;\r
+\r
+//\r
+// NvmExpress Admin Create I/O Completion Queue\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Qid:16; /* Queue Identifier */\r
+ UINT32 Qsize:16; /* Queue Size */\r
+\r
+ //\r
+ // CDW 11\r
+ //\r
+ UINT32 Pc:1; /* Physically Contiguous */\r
+ UINT32 Ien:1; /* Interrupts Enabled */\r
+ UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Iv:16; /* Interrupt Vector */\r
+} NVME_ADMIN_CRIOCQ;\r
+\r
+//\r
+// NvmExpress Admin Create I/O Submission Queue\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Qid:16; /* Queue Identifier */\r
+ UINT32 Qsize:16; /* Queue Size */\r
+\r
+ //\r
+ // CDW 11\r
+ //\r
+ UINT32 Pc:1; /* Physically Contiguous */\r
+ UINT32 Qprio:2; /* Queue Priority */\r
+ UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Cqid:16; /* Completion Queue ID */\r
+} NVME_ADMIN_CRIOSQ;\r
+\r
+//\r
+// NvmExpress Admin Delete I/O Completion Queue\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT16 Qid;\r
+ UINT16 Rsvd1;\r
+} NVME_ADMIN_DEIOCQ;\r
+\r
+//\r
+// NvmExpress Admin Delete I/O Submission Queue\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT16 Qid;\r
+ UINT16 Rsvd1;\r
+} NVME_ADMIN_DEIOSQ;\r
+\r
+//\r
+// NvmExpress Admin Abort Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Sqid:16; /* Submission Queue identifier */\r
+ UINT32 Cid:16; /* Command Identifier */\r
+} NVME_ADMIN_ABORT;\r
+\r
+//\r
+// NvmExpress Admin Firmware Activate Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Fs:3; /* Submission Queue identifier */\r
+ UINT32 Aa:2; /* Command Identifier */\r
+ UINT32 Rsvd1:27;\r
+} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
+\r
+//\r
+// NvmExpress Admin Firmware Image Download Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Numd; /* Number of Dwords */\r
+ //\r
+ // CDW 11\r
+ //\r
+ UINT32 Ofst; /* Offset */\r
+} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
+\r
+//\r
+// NvmExpress Admin Get Features Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Fid:8; /* Feature Identifier */\r
+ UINT32 Sel:3; /* Select */\r
+ UINT32 Rsvd1:21;\r
+} NVME_ADMIN_GET_FEATURES;\r
+\r
+//\r
+// NvmExpress Admin Get Log Page Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Lid:8; /* Log Page Identifier */\r
+ #define LID_ERROR_INFO\r
+ #define LID_SMART_INFO\r
+ #define LID_FW_SLOT_INFO\r
+ UINT32 Rsvd1:8;\r
+ UINT32 Numd:12; /* Number of Dwords */\r
+ UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
+} NVME_ADMIN_GET_LOG_PAGE;\r
+\r
+//\r
+// NvmExpress Admin Set Features Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Fid:8; /* Feature Identifier */\r
+ UINT32 Rsvd1:23;\r
+ UINT32 Sv:1; /* Save */\r
+} NVME_ADMIN_SET_FEATURES;\r
+\r
+//\r
+// NvmExpress Admin Format NVM Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Lbaf:4; /* LBA Format */\r
+ UINT32 Ms:1; /* Metadata Settings */\r
+ UINT32 Pi:3; /* Protection Information */\r
+ UINT32 Pil:1; /* Protection Information Location */\r
+ UINT32 Ses:3; /* Secure Erase Settings */\r
+ UINT32 Rsvd1:20;\r
+} NVME_ADMIN_FORMAT_NVM;\r
+\r
+//\r
+// NvmExpress Admin Security Receive Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Rsvd1:8;\r
+ UINT32 Spsp:16; /* SP Specific */\r
+ UINT32 Secp:8; /* Security Protocol */\r
+ //\r
+ // CDW 11\r
+ //\r
+ UINT32 Al; /* Allocation Length */\r
+} NVME_ADMIN_SECURITY_RECEIVE;\r
+\r
+//\r
+// NvmExpress Admin Security Send Command\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 10\r
+ //\r
+ UINT32 Rsvd1:8;\r
+ UINT32 Spsp:16; /* SP Specific */\r
+ UINT32 Secp:8; /* Security Protocol */\r
+ //\r
+ // CDW 11\r
+ //\r
+ UINT32 Tl; /* Transfer Length */\r
+} NVME_ADMIN_SECURITY_SEND;\r
+\r
+typedef union {\r
+ NVME_ADMIN_IDENTIFY Identify;\r
+ NVME_ADMIN_CRIOCQ CrIoCq;\r
+ NVME_ADMIN_CRIOSQ CrIoSq;\r
+ NVME_ADMIN_DEIOCQ DeIoCq;\r
+ NVME_ADMIN_DEIOSQ DeIoSq;\r
+ NVME_ADMIN_ABORT Abort;\r
+ NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r
+ NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r
+ NVME_ADMIN_GET_FEATURES GetFeatures;\r
+ NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r
+ NVME_ADMIN_SET_FEATURES SetFeatures;\r
+ NVME_ADMIN_FORMAT_NVM FormatNvm;\r
+ NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r
+ NVME_ADMIN_SECURITY_SEND SecuritySend;\r
+} NVME_ADMIN_CMD;\r
+\r
+typedef struct {\r
+ UINT32 Cdw10;\r
+ UINT32 Cdw11;\r
+ UINT32 Cdw12;\r
+ UINT32 Cdw13;\r
+ UINT32 Cdw14;\r
+ UINT32 Cdw15;\r
+} NVME_RAW;\r
+\r
+typedef union {\r
+ NVME_ADMIN_CMD Admin; // Union of Admin commands\r
+ NVME_CMD Nvm; // Union of Nvm commands\r
+ NVME_RAW Raw;\r
+} NVME_PAYLOAD;\r
+\r
+//\r
+// Submission Queue\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 0, Common to all comnmands\r
+ //\r
+ UINT8 Opc; // Opcode\r
+ UINT8 Fuse:2; // Fused Operation\r
+ UINT8 Rsvd1:5;\r
+ UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
+ UINT16 Cid; // Command Identifier\r
+\r
+ //\r
+ // CDW 1\r
+ //\r
+ UINT32 Nsid; // Namespace Identifier\r
+\r
+ //\r
+ // CDW 2,3\r
+ //\r
+ UINT64 Rsvd2;\r
+\r
+ //\r
+ // CDW 4,5\r
+ //\r
+ UINT64 Mptr; // Metadata Pointer\r
+\r
+ //\r
+ // CDW 6-9\r
+ //\r
+ UINT64 Prp[2]; // First and second PRP entries\r
+\r
+ NVME_PAYLOAD Payload;\r
+\r
+} NVME_SQ;\r
+\r
+//\r
+// Completion Queue\r
+//\r
+typedef struct {\r
+ //\r
+ // CDW 0\r
+ //\r
+ UINT32 Dword0;\r
+ //\r
+ // CDW 1\r
+ //\r
+ UINT32 Rsvd1;\r
+ //\r
+ // CDW 2\r
+ //\r
+ UINT16 Sqhd; // Submission Queue Head Pointer\r
+ UINT16 Sqid; // Submission Queue Identifier\r
+ //\r
+ // CDW 3\r
+ //\r
+ UINT16 Cid; // Command Identifier\r
+ UINT16 Pt:1; // Phase Tag\r
+ UINT16 Sc:8; // Status Code\r
+ UINT16 Sct:3; // Status Code Type\r
+ UINT16 Rsvd2:2;\r
+ UINT16 Mo:1; // More\r
+ UINT16 Dnr:1; // Retry\r
+} NVME_CQ;\r
+\r
+//\r
+// Nvm Express Admin cmd opcodes\r
+//\r
+#define NVME_ADMIN_CRIOSQ_OPC 1\r
+#define NVME_ADMIN_CRIOCQ_OPC 5\r
+#define NVME_ADMIN_IDENTIFY_OPC 6\r
+\r
+#define NVME_IO_FLUSH_OPC 0\r
+#define NVME_IO_WRITE_OPC 1\r
+#define NVME_IO_READ_OPC 2\r
+\r
+//\r
+// Offset from the beginning of private data queue buffer\r
+//\r
+#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE\r
+\r
+/**\r
+ Initialize the Nvm Express controller.\r
+\r
+ @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
+\r
+ @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.\r
+ @retval Others A device error occurred while initializing the controller.\r
+\r
+**/\r
+EFI_STATUS\r
+NvmeControllerInit (\r
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private\r
+ );\r
+\r
+/**\r
+ Get identify controller data.\r
+\r
+ @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
+ @param Buffer The buffer used to store the identify controller data.\r
+\r
+ @return EFI_SUCCESS Successfully get the identify controller data.\r
+ @return EFI_DEVICE_ERROR Fail to get the identify controller data.\r
+\r
+**/\r
+EFI_STATUS\r
+NvmeIdentifyController (\r
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Get specified identify namespace data.\r
+\r
+ @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.\r
+ @param NamespaceId The specified namespace identifier.\r
+ @param Buffer The buffer used to store the identify namespace data.\r
+\r
+ @return EFI_SUCCESS Successfully get the identify namespace data.\r
+ @return EFI_DEVICE_ERROR Fail to get the identify namespace data.\r
+\r
+**/\r
+EFI_STATUS\r
+NvmeIdentifyNamespace (\r
+ IN NVME_CONTROLLER_PRIVATE_DATA *Private,\r
+ IN UINT32 NamespaceId,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+#pragma pack()\r
+\r
+#endif\r
+\r
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