// these two cmds are special which requires their data buffer must support simultaneous access by both the\r
// processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r
//\r
- if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_OPC) && (Sq->Opc != NVME_ADMIN_CRIOSQ_OPC)) {\r
+ if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {\r
if ((Sq->Opc & BIT0) != 0) {\r
Flag = EfiPciIoOperationBusMasterRead;\r
} else {\r
}\r
}\r
\r
- if ((Private->CqHdbl[QueueType].Cqh ^= 1) == 0) {\r
- Private->Pt[QueueType] ^= 1;\r
- }\r
-\r
//\r
- // Copy the Respose Queue entry for this command to the callers response buffer\r
+ // Check the NVMe cmd execution result\r
//\r
- CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
+ if (Status != EFI_TIMEOUT) {\r
+ if ((Cq->Sct == 0) && (Cq->Sc == 0)) {\r
+ Status = EFI_SUCCESS;\r
+ } else {\r
+ Status = EFI_DEVICE_ERROR;\r
+ //\r
+ // Copy the Respose Queue entry for this command to the callers response buffer\r
+ //\r
+ CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r
+ \r
+ //\r
+ // Dump every completion entry status for debugging.\r
+ //\r
+ DEBUG_CODE_BEGIN();\r
+ NvmeDumpStatus(Cq);\r
+ DEBUG_CODE_END();\r
+ }\r
+ }\r
\r
- //\r
- // Dump every completion entry status for debugging.\r
- //\r
- DEBUG_CODE_BEGIN();\r
- NvmeDumpStatus(Cq);\r
- DEBUG_CODE_END();\r
+ if ((Private->CqHdbl[QueueType].Cqh ^= 1) == 0) {\r
+ Private->Pt[QueueType] ^= 1;\r
+ }\r
\r
Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueType]);\r
PciIo->Mem.Write (\r