Update all the code to consume the ConvertDevicePathToText, ConvertDevicePathNodeToTe...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciBus.h

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 722f31d03c5c4ea7d5b8bab858fc153c2ebaa1bb..fc62a251c231d28f9df0a93a2d2a80ea7a676b73 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -1,8 +1,8 @@
 /** @file\r
   Header files and data structures needed by PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
@@ -104,7 +104,7 @@ struct _PCI_BAR {
   PCI_BAR_TYPE  BarType;\r
   BOOLEAN       Prefetchable;\r
   UINT8         MemType;\r
-  UINT8         Offset;\r
+  UINT16        Offset;\r
 };\r
 \r
 //\r
@@ -127,6 +127,12 @@ struct _PCI_BAR {
 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
 \r
+#define RB_IO_RANGE                           1\r
+#define RB_MEM32_RANGE                        2\r
+#define RB_PMEM32_RANGE                       3\r
+#define RB_MEM64_RANGE                        4\r
+#define RB_PMEM64_RANGE                       5\r
+\r
 #define PPB_BAR_0                             0\r
 #define PPB_BAR_1                             1\r
 #define PPB_IO_RANGE                          2\r
@@ -223,6 +229,11 @@ struct _PCI_IO_DEVICE {
   //\r
   UINT32                                    Decodes;\r
 \r
+  //\r
+  // TRUE if the ROM image is from the PCI Option ROM BAR\r
+  //\r
+  BOOLEAN                                   EmbeddedRom;\r
+\r
   //\r
   // The OptionRom Size\r
   //\r
@@ -238,6 +249,11 @@ struct _PCI_IO_DEVICE {
   //\r
   BOOLEAN                                   AllOpRomProcessed;\r
 \r
+  //\r
+  // TRUE if the ROM image contains EFI OpROM\r
+  //\r
+  BOOLEAN                                   HasEfiOpRom;\r
+\r
   //\r
   // TRUE if there is any EFI driver in the OptionRom\r
   //\r
@@ -256,6 +272,11 @@ struct _PCI_IO_DEVICE {
   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;\r
   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;\r
 \r
+  //\r
+  // Bus number ranges for a PCI Root Bridge device\r
+  //\r
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;\r
+\r
   BOOLEAN                                   IsPciExp;\r
   //\r
   // For SR-IOV\r
@@ -268,6 +289,12 @@ struct _PCI_IO_DEVICE {
   UINT32                                    SystemPageSize;\r
   UINT16                                    InitialVFs;\r
   UINT16                                    ReservedBusNum;\r
+  //\r
+  // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
+  // but some chipsets support non-stardard I/O window aligments less than 4K.\r
+  // This field is used to support this case.\r
+  //\r
+  UINT16                                    BridgeIoAlignment;\r
 };\r
 \r
 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
@@ -298,8 +325,8 @@ extern UINT64                                       gAllOne;
 extern UINT64                                       gAllZero;\r
 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;\r
 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;\r
-\r
-\r
+extern BOOLEAN                                      mReserveIsaAliases;\r
+extern BOOLEAN                                      mReserveVgaAliases;\r
 \r
 /**\r
   Macro that checks whether device is a GFX device.\r