/** @file\r
PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
This routine is used to enumerate entire pci bus system\r
in a given platform.\r
\r
- @param Controller Parent controller handle.\r
+ @param Controller Parent controller handle.\r
+ @param HostBridgeHandle Host bridge handle.\r
\r
@retval EFI_SUCCESS PCI enumeration finished successfully.\r
@retval other Some error occurred when enumerating the pci bus system.\r
**/\r
EFI_STATUS\r
PciEnumerator (\r
- IN EFI_HANDLE Controller\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_HANDLE HostBridgeHandle\r
)\r
{\r
- EFI_HANDLE HostBridgeHandle;\r
EFI_STATUS Status;\r
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
-\r
- //\r
- // If PCI bus has already done the full enumeration, never do it again\r
- //\r
- if (!gFullEnumeration) {\r
- return PciEnumeratorLight (Controller);\r
- }\r
-\r
- //\r
- // Get the rootbridge Io protocol to find the host bridge handle\r
- //\r
- Status = gBS->OpenProtocol (\r
- Controller,\r
- &gEfiPciRootBridgeIoProtocolGuid,\r
- (VOID **) &PciRootBridgeIo,\r
- gPciBusDriverBinding.DriverBindingHandle,\r
- Controller,\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Get the host bridge handle\r
- //\r
- HostBridgeHandle = PciRootBridgeIo->ParentHandle;\r
\r
//\r
// Get the pci host bridge resource allocation protocol\r
return Status;\r
}\r
\r
- gFullEnumeration = FALSE;\r
-\r
- Status = gBS->InstallProtocolInterface (\r
- &HostBridgeHandle,\r
- &gEfiPciEnumerationCompleteProtocolGuid,\r
- EFI_NATIVE_INTERFACE,\r
- NULL\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
return EFI_SUCCESS;\r
}\r
\r
AddrRangeMin = Configuration1->AddrRangeMin;\r
Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;\r
Configuration2->AddrRangeMin = AddrRangeMin;\r
- \r
+\r
AddrLen = Configuration1->AddrLen;\r
Configuration1->AddrLen = Configuration2->AddrLen;\r
Configuration2->AddrLen = AddrLen;\r
Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
- } \r
+ }\r
\r
//\r
// Find the bus range which contains the higest bus number, then returns the number of buses\r
Configuration++;\r
Desc = Configuration->Desc;\r
Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;\r
- \r
+\r
//\r
// Set bus number\r
//\r
//\r
Configuration->Desc = Desc;\r
(Configuration - 1)->AddrLen = AddrLen;\r
- \r
+\r
return Status;\r
}\r
\r
Phase,\r
ChipsetEntry\r
);\r
- } \r
+ }\r
\r
Status = PciResAlloc->NotifyPhase (\r
PciResAlloc,\r
return EFI_INVALID_PARAMETER;\r
}\r
}\r
- \r
+\r
Status = gBS->OpenProtocol (\r
Controller,\r
&gEfiPciIoProtocolGuid,\r