/** @file\r
PCI emumeration support functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PciBus.h"\r
\r
+extern CHAR16 *mBarTypeStr[];\r
+\r
/**\r
This routine is used to check whether the pci device is present.\r
\r
\r
PciIoDevice = NULL;\r
\r
+ DEBUG ((\r
+ EFI_D_INFO,\r
+ "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",\r
+ IS_PCI_BRIDGE (Pci) ? L"PPB" :\r
+ IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :\r
+ L"PCI",\r
+ Bus, Device, Func\r
+ ));\r
+\r
if (!IS_PCI_BRIDGE (Pci)) {\r
\r
if (IS_CARDBUS_BRIDGE (Pci)) {\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Dump the PCI BAR information.\r
+\r
+ @param PciIoDevice PCI IO instance.\r
+**/\r
+VOID\r
+DumpPciBars (\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
+ )\r
+{\r
+ UINTN Index;\r
+\r
+ for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r
+ if (PciIoDevice->PciBar[Index].BarType == PciBarTypeUnknown) {\r
+ continue;\r
+ }\r
+\r
+ DEBUG ((\r
+ EFI_D_INFO,\r
+ " BAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",\r
+ Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],\r
+ PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset\r
+ ));\r
+ }\r
+\r
+ for (Index = 0; Index < PCI_MAX_BAR; Index++) {\r
+ if ((PciIoDevice->VfPciBar[Index].BarType == PciBarTypeUnknown) && (PciIoDevice->VfPciBar[Index].Length == 0)) {\r
+ continue;\r
+ }\r
+\r
+ DEBUG ((\r
+ EFI_D_INFO,\r
+ " VFBAR[%d]: Type = %s; Alignment = 0x%x;\tLength = 0x%x;\tOffset = 0x%02x\n",\r
+ Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],\r
+ PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset\r
+ ));\r
+ }\r
+ DEBUG ((EFI_D_INFO, "\n"));\r
+}\r
+\r
/**\r
Create PCI device instance for PCI device.\r
\r
Offset = PciIovParseVfBar (PciIoDevice, Offset, BarIndex);\r
}\r
}\r
+\r
+ DEBUG_CODE (DumpPciBars (PciIoDevice););\r
return PciIoDevice;\r
}\r
\r
UINT8 Value;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT8 Temp;\r
+ UINT32 PMemBaseLimit;\r
+ UINT16 PrefetchableMemoryBase;\r
+ UINT16 PrefetchableMemoryLimit;\r
\r
PciIoDevice = CreatePciIoDevice (\r
Bridge,\r
PciIoDevice,\r
0x24,\r
NULL,\r
- NULL\r
+ &PMemBaseLimit\r
);\r
\r
//\r
// Test if it supports 64 memory or not\r
//\r
- if (!EFI_ERROR (Status)) {\r
-\r
+ // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit\r
+ // registers:\r
+ // 0 - the bridge supports only 32 bit addresses.\r
+ // 1 - the bridge supports 64-bit addresses.\r
+ //\r
+ PrefetchableMemoryBase = (UINT16)(PMemBaseLimit & 0xffff);\r
+ PrefetchableMemoryLimit = (UINT16)(PMemBaseLimit >> 16);\r
+ if (!EFI_ERROR (Status) &&\r
+ (PrefetchableMemoryBase & 0x000f) == 0x0001 &&\r
+ (PrefetchableMemoryLimit & 0x000f) == 0x0001) {\r
Status = BarExisted (\r
PciIoDevice,\r
0x28,\r
\r
GetResourcePaddingPpb (PciIoDevice);\r
\r
+ DEBUG_CODE (DumpPciBars (PciIoDevice););\r
+\r
return PciIoDevice;\r
}\r
\r
EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |\r
EFI_BRIDGE_IO32_DECODE_SUPPORTED;\r
\r
+ DEBUG_CODE (DumpPciBars (PciIoDevice););\r
+\r
return PciIoDevice;\r
}\r
\r
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r
\r
- if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {\r
- Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
- Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;\r
+ if (IS_PCI_LPC (&PciIoDevice->Pci)) {\r
+ Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ Attributes |= (mReserveIsaAliases ? EFI_PCI_IO_ATTRIBUTE_ISA_IO : \\r
+ EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);\r
}\r
\r
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
//\r
Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO;\r
Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO;\r
+\r
+ if (mReserveVgaAliases) {\r
+ Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | \\r
+ EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16);\r
+ } else {\r
+ Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_VGA_IO | \\r
+ EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);\r
+ }\r
} else {\r
\r
if (IS_PCI_IDE (&PciIoDevice->Pci)) {\r
\r
if (IS_PCI_VGA (&PciIoDevice->Pci)) {\r
Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;\r
- Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO;\r
+ Attributes |= (mReserveVgaAliases ? EFI_PCI_IO_ATTRIBUTE_VGA_IO : \\r
+ EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);\r
}\r
}\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+ //\r
+ // Assume the PCI Root Bridge supports DAC\r
+ //\r
PciIoDevice->Supports |= (EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
- EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM);\r
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
\r
} else {\r
\r
UINT32 Value;\r
UINT32 OriginalValue;\r
UINT32 Mask;\r
- UINT32 Data;\r
- UINT8 Index;\r
EFI_STATUS Status;\r
\r
//\r
//\r
// Fix the length to support some spefic 64 bit BAR\r
//\r
- Data = Value;\r
- Index = 0;\r
- for (Data = Value; Data != 0; Data >>= 1) {\r
- Index ++;\r
- }\r
- Value |= ((UINT32)(-1) << Index); \r
+ Value |= ((UINT32) -1 << HighBitSet32 (Value));\r
\r
//\r
// Calculate the size of 64bit bar\r
UINT32 Value;\r
UINT32 OriginalValue;\r
UINT32 Mask;\r
- UINT32 Data;\r
- UINT8 Index;\r
EFI_STATUS Status;\r
\r
OriginalValue = 0;\r
//\r
// Fix the length to support some spefic 64 bit BAR\r
//\r
- Data = Value;\r
- Index = 0;\r
- for (Data = Value; Data != 0; Data >>= 1) {\r
- Index ++;\r
- }\r
- Value |= ((UINT32)(-1) << Index);\r
+ Value |= ((UINT32)(-1) << HighBitSet32 (Value));\r
\r
//\r
// Calculate the size of 64bit bar\r
);\r
DEBUG ((\r
EFI_D_INFO,\r
- "PCI B%x.D%x.F%x - ARI forwarding enabled\n",\r
- (UINTN)Bridge->BusNumber,\r
- (UINTN)Bridge->DeviceNumber,\r
- (UINTN)Bridge->FunctionNumber\r
+ " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",\r
+ Bridge->BusNumber,\r
+ Bridge->DeviceNumber,\r
+ Bridge->FunctionNumber\r
));\r
}\r
}\r
\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "PCI ARI B%x.D%x.F%x - ARI Cap offset - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- (UINTN)PciIoDevice->AriCapabilityOffset\r
- ));\r
+ DEBUG ((EFI_D_INFO, " ARI: CapOffset = 0x%x\n", PciIoDevice->AriCapabilityOffset));\r
}\r
}\r
\r
NULL\r
);\r
if (!EFI_ERROR (Status)) {\r
+ UINT32 SupportedPageSize;\r
UINT16 VFStride;\r
UINT16 FirstVFOffset;\r
UINT16 Data16;\r
EfiPciIoWidthUint32,\r
PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE,\r
1,\r
- &PciIoDevice->SystemPageSize\r
+ &SupportedPageSize\r
);\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "PCI SR-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- PciIoDevice->SystemPageSize\r
- ));\r
-\r
- PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & PciIoDevice->SystemPageSize);\r
+ PciIoDevice->SystemPageSize = (PcdGet32 (PcdSrIovSystemPageSize) & SupportedPageSize);\r
ASSERT (PciIoDevice->SystemPageSize != 0);\r
\r
PciIo->Pci.Write (\r
1,\r
&PciIoDevice->SystemPageSize\r
);\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "PCI SR-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- PciIoDevice->SystemPageSize\r
- ));\r
//\r
// Adjust SystemPageSize for Alignment usage later\r
//\r
1,\r
&FirstVFOffset\r
);\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "PCI SR-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- (UINTN)FirstVFOffset\r
- ));\r
-\r
PciIo->Pci.Read (\r
PciIo,\r
EfiPciIoWidthUint16,\r
1,\r
&PciIoDevice->InitialVFs\r
);\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "PCI SR-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- (UINTN)PciIoDevice->InitialVFs\r
- ));\r
-\r
PciIo->Pci.Read (\r
PciIo,\r
EfiPciIoWidthUint16,\r
1,\r
&VFStride\r
);\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "PCI SR-IOV B%x.D%x.F%x - VFStride - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- (UINTN)VFStride\r
- ));\r
-\r
//\r
// Calculate LastVF\r
//\r
// Calculate ReservedBusNum for this PF\r
//\r
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);\r
+\r
DEBUG ((\r
EFI_D_INFO,\r
- "PCI SR-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- (UINTN)PciIoDevice->ReservedBusNum\r
+ " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",\r
+ SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset\r
));\r
-\r
DEBUG ((\r
EFI_D_INFO,\r
- "PCI SR-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- (UINTN)PciIoDevice->SrIovCapabilityOffset\r
+ " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",\r
+ PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice->SrIovCapabilityOffset\r
));\r
}\r
}\r
NULL\r
);\r
if (!EFI_ERROR (Status)) {\r
- DEBUG ((\r
- EFI_D_INFO,\r
- "PCI MR-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",\r
- (UINTN)Bus,\r
- (UINTN)Device,\r
- (UINTN)Func,\r
- (UINTN)PciIoDevice->MrIovCapabilityOffset\r
- ));\r
+ DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice->MrIovCapabilityOffset));\r
}\r
}\r
\r
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