MdeModulePkg: Clean up source files

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciEnumeratorSupport.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index ecda088814a3c846f17615876314f8036b2de2ca..cfd291ef7d9095db00592e5a9778d38404829007 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI emumeration support functions implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
@@ -1254,9 +1254,11 @@ DetermineDeviceAttribute (
     PciSetDeviceAttribute (PciIoDevice, OldCommand, OldBridgeControl, EFI_SET_ATTRIBUTES);\r
 \r
     //\r
-    // Enable other supported attributes but not defined in PCI_IO_PROTOCOL\r
-    //\r
-    PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
+    // Enable other PCI supported attributes but not defined in PCI_IO_PROTOCOL\r
+    // For PCI Express devices, Memory Write and Invalidate is hardwired to 0b so only enable it for PCI devices.\r
+    if (!PciIoDevice->IsPciExp) {\r
+      PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
+    }\r
   }\r
 \r
   FastB2BSupport = TRUE;\r
@@ -1340,8 +1342,7 @@ UpdatePciInfo (
   )\r
 {\r
   EFI_STATUS                        Status;\r
-  UINT64                            BarIndex;\r
-  UINT64                            BarEndIndex;\r
+  UINTN                             BarIndex;\r
   BOOLEAN                           SetFlag;\r
   VOID                              *Configuration;\r
   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
@@ -1395,24 +1396,19 @@ UpdatePciInfo (
       break;\r
     }\r
 \r
-    BarIndex    = Ptr->AddrTranslationOffset;\r
-    BarEndIndex = BarIndex;\r
-\r
-    //\r
-    // Update all the bars in the device\r
-    // Compare against 0xFF is to keep backward compatibility.\r
-    //\r
-    if ((BarIndex == MAX_UINT64) || (BarIndex == 0xFF)) {\r
-      BarIndex    = 0;\r
-      BarEndIndex = PCI_MAX_BAR - 1;\r
-    }\r
-\r
-    if (BarIndex >= PCI_MAX_BAR) {\r
-      Ptr++;\r
-      continue;\r
-    }\r
+    for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex++) {\r
+      if ((Ptr->AddrTranslationOffset != MAX_UINT64) &&\r
+          (Ptr->AddrTranslationOffset != MAX_UINT8) &&\r
+          (Ptr->AddrTranslationOffset != BarIndex)\r
+          ) {\r
+        //\r
+        // Skip updating when AddrTranslationOffset is not MAX_UINT64 or MAX_UINT8 (wide match).\r
+        // Skip updating when current BarIndex doesn't equal to AddrTranslationOffset.\r
+        // Comparing against MAX_UINT8 is to keep backward compatibility.\r
+        //\r
+        continue;\r
+      }\r
 \r
-    for (; BarIndex <= BarEndIndex; BarIndex++) {\r
       SetFlag = FALSE;\r
       switch (Ptr->ResType) {\r
       case ACPI_ADDRESS_SPACE_TYPE_MEM:\r
@@ -1740,7 +1736,7 @@ PciIovParseVfBar (
       break;\r
     }\r
   }\r
-  \r
+\r
   //\r
   // Check the length again so as to keep compatible with some special bars\r
   //\r
@@ -1749,7 +1745,7 @@ PciIovParseVfBar (
     PciIoDevice->VfPciBar[BarIndex].BaseAddress = 0;\r
     PciIoDevice->VfPciBar[BarIndex].Alignment   = 0;\r
   }\r
-  \r
+\r
   //\r
   // Increment number of bar\r
   //\r
@@ -2189,7 +2185,7 @@ CreatePciIoDevice (
       //\r
       ParentPciIo = &Bridge->PciIo;\r
       ParentPciIo->Pci.Read (\r
-                          ParentPciIo, \r
+                          ParentPciIo,\r
                           EfiPciIoWidthUint32,\r
                           Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,\r
                           1,\r