/** @file\r
EFI PCI IO protocol functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
NULL\r
};\r
\r
-/**\r
- Report a error Status code of PCI bus driver controller.\r
-\r
- @param PciIoDevice Pci device instance.\r
- @param Code Status code value.\r
-\r
-**/\r
-EFI_STATUS\r
-ReportErrorStatusCode (\r
- IN PCI_IO_DEVICE *PciIoDevice,\r
- IN EFI_STATUS_CODE_VALUE Code\r
- )\r
-{\r
- return REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
- EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
- Code,\r
- PciIoDevice->DevicePath\r
- );\r
-}\r
-\r
/**\r
Initializes a PCI I/O Instance.\r
\r
IN UINT64 *Offset\r
)\r
{\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
// If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX\r
// If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
//\r
- if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
+ if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {\r
Count = 1;\r
}\r
\r
{\r
UINT64 ExtendOffset;\r
\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if ((*Result & Mask) == Value || Delay == 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ do {\r
+ //\r
+ // Stall 10 us = 100 * 100ns\r
+ //\r
+ gBS->Stall (10);\r
+\r
+ Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ if (Delay <= 100) {\r
+ return EFI_TIMEOUT;\r
+ }\r
+ Delay -= 100;\r
+ } while (TRUE);\r
+ }\r
+ }\r
+ \r
Status = PciIoDevice->PciRootBridgeIo->PollMem (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Width < 0 || Width > EfiPciIoWidthUint64) {\r
+ if ((UINT32)Width > EfiPciIoWidthUint64) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if ((*Result & Mask) == Value || Delay == 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ do {\r
+ //\r
+ // Stall 10 us = 100 * 100ns\r
+ //\r
+ gBS->Stall (10);\r
+\r
+ Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ if (Delay <= 100) {\r
+ return EFI_TIMEOUT;\r
+ }\r
+ Delay -= 100;\r
+ } while (TRUE);\r
+ }\r
+ }\r
+ \r
Status = PciIoDevice->PciRootBridgeIo->PollIo (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Count *= (UINTN)(1 << (Width & 0x03));\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+ }\r
+ } \r
+ \r
+\r
Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Count *= (UINTN)(1 << (Width & 0x03));\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+ }\r
+ }\r
+\r
Status = PciIoDevice->PciRootBridgeIo->Mem.Write (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Count *= (UINTN)(1 << (Width & 0x03));\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+ }\r
+ } \r
+\r
Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Count *= (UINTN)(1 << (Width & 0x03));\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+ }\r
+ } \r
+\r
Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+ \r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Count *= (UINTN)(1 << (Width & 0x03));\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+ }\r
+ } \r
\r
Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r
PciIoDevice->PciRootBridgeIo,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
return Status;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Count *= (UINTN)(1 << (Width & 0x03));\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+ }\r
+ } \r
+ \r
Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiPciIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+ // \r
+ if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+ if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+ Count *= (UINTN)(1 << (Width & 0x03));\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+ }\r
+ } \r
+\r
Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r
PciIoDevice->PciRootBridgeIo,\r
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
- if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {\r
+ if ((UINT32)Operation >= EfiPciIoOperationMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
PciIoDevice->PciRootBridgeIo\r
);\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
return EFI_UNSUPPORTED;\r
}\r
\r
+ //\r
+ // Mask off attributes not supported by PCI root bridge.\r
+ //\r
+ Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |\r
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);\r
+\r
//\r
// Record the new attribute of the Root Bridge\r
//\r
);\r
}\r
\r
+ //\r
+ // Check VGA and VGA16, they can not be set at the same time\r
+ //\r
+ if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
+ ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||\r
+ ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
+ ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
//\r
// If no attributes can be supported, then return.\r
// Otherwise, set the attributes that it can support.\r
Command = 0;\r
BridgeControl = 0;\r
\r
- //\r
- // Check VGA and VGA16, they can not be set at the same time\r
- //\r
- if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
- ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||\r
- ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||\r
- ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
- (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
//\r
// For PPB & P2C, set relevant attribute bits\r
//\r
}\r
\r
if (EFI_ERROR (Status)) {\r
- ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,\r
+ PciIoDevice->DevicePath\r
+ );\r
}\r
\r
return Status;\r
OUT VOID **Resources OPTIONAL\r
)\r
{\r
-\r
UINT8 *Configuration;\r
- UINT8 NumConfig;\r
PCI_IO_DEVICE *PciIoDevice;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
- EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
-\r
- NumConfig = 0;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AddressSpace;\r
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (BarIndex >= PCI_MAX_BAR) {\r
+ if ((BarIndex >= PCI_MAX_BAR) || (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown)) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (Resources != NULL) {\r
-\r
- if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {\r
- NumConfig = 1;\r
- }\r
-\r
- Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
if (Configuration == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
-\r
- if (NumConfig == 1) {\r
- Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
+ AddressSpace = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
\r
- Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
- Ptr->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r
- Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r
+ AddressSpace->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ AddressSpace->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
\r
- switch (PciIoDevice->PciBar[BarIndex].BarType) {\r
- case PciBarTypeIo16:\r
- case PciBarTypeIo32:\r
- //\r
- // Io\r
- //\r
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
- break;\r
+ AddressSpace->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
+ AddressSpace->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r
+ AddressSpace->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r
\r
- case PciBarTypeMem32:\r
- //\r
- // Mem\r
- //\r
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- //\r
- // 32 bit\r
- //\r
- Ptr->AddrSpaceGranularity = 32;\r
- break;\r
+ switch (PciIoDevice->PciBar[BarIndex].BarType) {\r
+ case PciBarTypeIo16:\r
+ case PciBarTypeIo32:\r
+ //\r
+ // Io\r
+ //\r
+ AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
+ break;\r
\r
- case PciBarTypePMem32:\r
- //\r
- // Mem\r
- //\r
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- //\r
- // prefechable\r
- //\r
- Ptr->SpecificFlag = 0x6;\r
- //\r
- // 32 bit\r
- //\r
- Ptr->AddrSpaceGranularity = 32;\r
- break;\r
+ case PciBarTypeMem32:\r
+ //\r
+ // Mem\r
+ //\r
+ AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ //\r
+ // 32 bit\r
+ //\r
+ AddressSpace->AddrSpaceGranularity = 32;\r
+ break;\r
\r
- case PciBarTypeMem64:\r
- //\r
- // Mem\r
- //\r
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- //\r
- // 64 bit\r
- //\r
- Ptr->AddrSpaceGranularity = 64;\r
- break;\r
+ case PciBarTypePMem32:\r
+ //\r
+ // Mem\r
+ //\r
+ AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ //\r
+ // prefechable\r
+ //\r
+ AddressSpace->SpecificFlag = 0x6;\r
+ //\r
+ // 32 bit\r
+ //\r
+ AddressSpace->AddrSpaceGranularity = 32;\r
+ break;\r
\r
- case PciBarTypePMem64:\r
- //\r
- // Mem\r
- //\r
- Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- //\r
- // prefechable\r
- //\r
- Ptr->SpecificFlag = 0x6;\r
- //\r
- // 64 bit\r
- //\r
- Ptr->AddrSpaceGranularity = 64;\r
- break;\r
+ case PciBarTypeMem64:\r
+ //\r
+ // Mem\r
+ //\r
+ AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ //\r
+ // 64 bit\r
+ //\r
+ AddressSpace->AddrSpaceGranularity = 64;\r
+ break;\r
\r
- default:\r
- break;\r
- }\r
+ case PciBarTypePMem64:\r
+ //\r
+ // Mem\r
+ //\r
+ AddressSpace->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ //\r
+ // prefechable\r
+ //\r
+ AddressSpace->SpecificFlag = 0x6;\r
+ //\r
+ // 64 bit\r
+ //\r
+ AddressSpace->AddrSpaceGranularity = 64;\r
+ break;\r
\r
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
+ default:\r
+ break;\r
}\r
\r
//\r
// put the checksum\r
//\r
- PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);\r
- PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
- PtrEnd->Checksum = 0;\r
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AddressSpace + 1);\r
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ End->Checksum = 0;\r
\r
- *Resources = Configuration;\r
+ *Resources = Configuration;\r
}\r
\r
return EFI_SUCCESS;\r
projects / mirror_edk2.git / blobdiff