Clean ISA_IO/ISA_IO_16 and VGA_IO/VGA_IO_16 attribute usage in PCI bus driver/PCI...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciIo.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index 5cc59672458faba94090a945ceb9e639a8e851e8..5f6d3763e9d3fdd9c17320eb0259335727449031 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1,8 +1,8 @@
 /** @file\r
   EFI PCI IO protocol functions implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
@@ -128,7 +128,7 @@ PciIoVerifyBarAccess (
   // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX\r
   // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
   //\r
-  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
+  if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {\r
     Count = 1;\r
   }\r
 \r
@@ -248,6 +248,39 @@ PciIoPollMem (
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Status  = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
+      if (EFI_ERROR (Status)) {\r
+        return Status;\r
+      }\r
+      if ((*Result & Mask) == Value || Delay == 0) {\r
+        return EFI_SUCCESS;\r
+      }\r
+      do {\r
+        //\r
+        // Stall 10 us = 100 * 100ns\r
+        //\r
+        gBS->Stall (10);\r
+\r
+        Status  = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);\r
+        if (EFI_ERROR (Status)) {\r
+          return Status;\r
+        }\r
+        if ((*Result & Mask) == Value) {\r
+          return EFI_SUCCESS;\r
+        }\r
+        if (Delay <= 100) {\r
+          return EFI_TIMEOUT;\r
+        }\r
+        Delay -= 100;\r
+      } while (TRUE);\r
+    }\r
+  }\r
+  \r
   Status = PciIoDevice->PciRootBridgeIo->PollMem (\r
                                            PciIoDevice->PciRootBridgeIo,\r
                                            (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -314,6 +347,39 @@ PciIoPollIo (
     return EFI_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Status  = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
+      if (EFI_ERROR (Status)) {\r
+        return Status;\r
+      }\r
+      if ((*Result & Mask) == Value || Delay == 0) {\r
+        return EFI_SUCCESS;\r
+      }\r
+      do {\r
+        //\r
+        // Stall 10 us = 100 * 100ns\r
+        //\r
+        gBS->Stall (10);\r
+\r
+        Status  = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);\r
+        if (EFI_ERROR (Status)) {\r
+          return Status;\r
+        }\r
+        if ((*Result & Mask) == Value) {\r
+          return EFI_SUCCESS;\r
+        }\r
+        if (Delay <= 100) {\r
+          return EFI_TIMEOUT;\r
+        }\r
+        Delay -= 100;\r
+      } while (TRUE);\r
+    }\r
+  }\r
+  \r
   Status = PciIoDevice->PciRootBridgeIo->PollIo (\r
                                            PciIoDevice->PciRootBridgeIo,\r
                                            (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -380,6 +446,17 @@ PciIoMemRead (
     return EFI_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Count *=  (UINTN)(1 << (Width & 0x03));\r
+      Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+    }\r
+  }  \r
+  \r
+\r
   Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r
                                               PciIoDevice->PciRootBridgeIo,\r
                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -444,6 +521,16 @@ PciIoMemWrite (
     return EFI_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Count *=  (UINTN)(1 << (Width & 0x03));\r
+      Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+    }\r
+  }\r
+\r
   Status = PciIoDevice->PciRootBridgeIo->Mem.Write (\r
                                               PciIoDevice->PciRootBridgeIo,\r
                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -508,6 +595,16 @@ PciIoIoRead (
     return EFI_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Count *=  (UINTN)(1 << (Width & 0x03));\r
+      Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+    }\r
+  }    \r
+\r
   Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r
                                               PciIoDevice->PciRootBridgeIo,\r
                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -572,6 +669,16 @@ PciIoIoWrite (
     return EFI_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Count *=  (UINTN)(1 << (Width & 0x03));\r
+      Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+    }\r
+  }  \r
+\r
   Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r
                                               PciIoDevice->PciRootBridgeIo,\r
                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -626,6 +733,16 @@ PciIoConfigRead (
   if (EFI_ERROR (Status)) {\r
     return Status;\r
   }\r
+  \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Count *=  (UINTN)(1 << (Width & 0x03));\r
+      Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+    }\r
+  }    \r
 \r
   Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r
                                                PciIoDevice->PciRootBridgeIo,\r
@@ -682,6 +799,16 @@ PciIoConfigWrite (
     return Status;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Count *=  (UINTN)(1 << (Width & 0x03));\r
+      Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+    }\r
+  }  \r
+  \r
   Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r
                                               PciIoDevice->PciRootBridgeIo,\r
                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -767,6 +894,16 @@ PciIoCopyMem (
     return EFI_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // If request is not aligned, then convert request to EfiPciIoWithXXXUint8\r
+  //  \r
+  if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {\r
+    if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {\r
+      Count *=  (UINTN)(1 << (Width & 0x03));\r
+      Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));\r
+    }\r
+  }  \r
+\r
   Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r
                                           PciIoDevice->PciRootBridgeIo,\r
                                           (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
@@ -1131,6 +1268,13 @@ ModifyRootBridgeAttributes (
     return EFI_UNSUPPORTED;\r
   }\r
 \r
+  //\r
+  // Mask off EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE & \r
+  // EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM, which are not supported by PCI root bridge.\r
+  //\r
+  Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |\r
+                          EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM);\r
+\r
   //\r
   // Record the new attribute of the Root Bridge\r
   //\r
@@ -1385,6 +1529,38 @@ PciIoAttributes (
       );\r
   }\r
 \r
+  //\r
+  // Check VGA and VGA16, they can not be set at the same time\r
+  //\r
+  if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0         &&\r
+       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0)         ||\r
+      ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0         &&\r
+       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||\r
+      ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
+       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0)         ||\r
+      ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
+       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // workaround for PCI drivers which always set ISA_IO or VGA_IO attribute without detecting support of\r
+  // ISA_IO/ISA_IO_16 or VGA_IO/VGA_IO_16 to maintain backward-compatibility.\r
+  //\r
+  if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0) && \r
+      ((PciIoDevice->Supports & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) \\r
+        == EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) {\r
+    Attributes &= ~(UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_IO;\r
+    Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16;\r
+  }\r
+\r
+  if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0) && \r
+      ((PciIoDevice->Supports & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) \\r
+        == EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) {\r
+    Attributes &= ~(UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r
+    Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+  }\r
+\r
   //\r
   // If no attributes can be supported, then return.\r
   // Otherwise, set the attributes that it can support.\r
@@ -1405,20 +1581,6 @@ PciIoAttributes (
   Command       = 0;\r
   BridgeControl = 0;\r
 \r
-  //\r
-  // Check VGA and VGA16, they can not be set at the same time\r
-  //\r
-  if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0         &&\r
-       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0)         ||\r
-      ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0         &&\r
-       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||\r
-      ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
-       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0)         ||\r
-      ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&\r
-       (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {\r
-    return EFI_UNSUPPORTED;\r
-  }\r
-\r
   //\r
   // For PPB & P2C, set relevant attribute bits\r
   //\r
@@ -1637,7 +1799,7 @@ PciIoGetBarAttributes (
 \r
     if (NumConfig == 1) {\r
       Ptr->Desc         = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
-      Ptr->Len          = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+      Ptr->Len          = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);\r
 \r
       Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
       Ptr->AddrLen      = PciIoDevice->PciBar[BarIndex].Length;\r