MdeModulePkg/AtaAtapiPassThru: Revert patch to disable Bus Master

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciIo.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index f72598d3ae680fa05ea400ae2922ed56d287ea89..cc7125e4fc3c00f924fc7ea11d482f785219cd14 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1,7 +1,7 @@
 /** @file\r
   EFI PCI IO protocol functions implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "PciBus.h"\r
 \r
+extern EDKII_IOMMU_PROTOCOL                          *mIoMmuProtocol;\r
+\r
 //\r
 // Pci Io Protocol Interface\r
 //\r
@@ -965,8 +967,10 @@ PciIoMap (
   OUT    VOID                           **Mapping\r
   )\r
 {\r
-  EFI_STATUS    Status;\r
-  PCI_IO_DEVICE *PciIoDevice;\r
+  EFI_STATUS                                 Status;\r
+  PCI_IO_DEVICE                              *PciIoDevice;\r
+  UINT64                                     IoMmuAttribute;\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  RootBridgeIoOperation;\r
 \r
   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
 \r
@@ -978,13 +982,14 @@ PciIoMap (
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
+  RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;\r
   if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r
-    Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);\r
+    RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + EfiPciOperationBusMasterRead64);\r
   }\r
 \r
   Status = PciIoDevice->PciRootBridgeIo->Map (\r
                                           PciIoDevice->PciRootBridgeIo,\r
-                                          (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,\r
+                                          RootBridgeIoOperation,\r
                                           HostAddress,\r
                                           NumberOfBytes,\r
                                           DeviceAddress,\r
@@ -999,6 +1004,31 @@ PciIoMap (
       );\r
   }\r
 \r
+  if (mIoMmuProtocol != NULL) {\r
+    if (!EFI_ERROR (Status)) {\r
+      switch (Operation) {\r
+      case EfiPciIoOperationBusMasterRead:\r
+        IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;\r
+        break;\r
+      case EfiPciIoOperationBusMasterWrite:\r
+        IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;\r
+        break;\r
+      case EfiPciIoOperationBusMasterCommonBuffer:\r
+        IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;\r
+        break;\r
+      default:\r
+        ASSERT(FALSE);\r
+        return EFI_INVALID_PARAMETER;\r
+      }\r
+      mIoMmuProtocol->SetAttribute (\r
+                        mIoMmuProtocol,\r
+                        PciIoDevice->Handle,\r
+                        *Mapping,\r
+                        IoMmuAttribute\r
+                        );\r
+    }\r
+  }\r
+\r
   return Status;\r
 }\r
 \r
@@ -1024,6 +1054,15 @@ PciIoUnmap (
 \r
   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
 \r
+  if (mIoMmuProtocol != NULL) {\r
+    mIoMmuProtocol->SetAttribute (\r
+                      mIoMmuProtocol,\r
+                      PciIoDevice->Handle,\r
+                      Mapping,\r
+                      0\r
+                      );\r
+  }\r
+\r
   Status = PciIoDevice->PciRootBridgeIo->Unmap (\r
                                           PciIoDevice->PciRootBridgeIo,\r
                                           Mapping\r
@@ -1799,12 +1838,12 @@ GetMmioAddressTranslationOffset (
                                 base address for resource range. The legal range for this field is 0..5.\r
   @param  Supports              A pointer to the mask of attributes that this PCI controller supports\r
                                 setting for this BAR with SetBarAttributes().\r
-  @param  Resources             A pointer to the ACPI 2.0 resource descriptors that describe the current\r
+  @param  Resources             A pointer to the resource descriptors that describe the current\r
                                 configuration of this BAR of the PCI controller.\r
 \r
   @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI\r
                                 controller supports are returned in Supports. If Resources\r
-                                is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
+                                is not NULL, then the resource descriptors that the PCI\r
                                 controller is currently using are returned in Resources.\r
   @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.\r