--- /dev/null
+/** @file\r
+ EFI PCI IO protocol functions declaration for PCI Bus module.\r
+\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _EFI_PCI_IO_PROTOCOL_H_\r
+#define _EFI_PCI_IO_PROTOCOL_H_\r
+\r
+/**\r
+ Initializes a PCI I/O Instance.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+\r
+**/\r
+VOID\r
+InitializePciIoInstance (\r
+ IN PCI_IO_DEVICE *PciIoDevice\r
+ );\r
+\r
+/**\r
+ Verifies access to a PCI Base Address Register (BAR).\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory or I/O operation to perform.\r
+ @param Type Operation type could be memory or I/O.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param Count The number of memory or I/O operations to perform.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
+ @retval EFI_SUCCESS Successfully verified.\r
+\r
+**/\r
+EFI_STATUS\r
+PciIoVerifyBarAccess (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT8 BarIndex,\r
+ IN PCI_BAR_TYPE Type,\r
+ IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN IN UINTN Count,\r
+ IN UINT64 *Offset\r
+ );\r
+\r
+/**\r
+ Verifies access to a PCI Configuration Header.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param Count The number of memory or I/O operations to perform.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
+\r
+ @retval EFI_INVALID_PARAMETER Invalid Width\r
+ @retval EFI_UNSUPPORTED Offset overflowed.\r
+ @retval EFI_SUCCESS Successfully verified.\r
+\r
+**/\r
+EFI_STATUS\r
+PciIoVerifyConfigAccess (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINTN Count,\r
+ IN UINT64 *Offset\r
+ );\r
+\r
+/**\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
+ satisfied or after a defined duration.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory operation.\r
+ @param Mask Mask used for the polling criteria.\r
+ @param Value The comparison value used for the polling exit criteria.\r
+ @param Delay The number of 100 ns units to poll.\r
+ @param Result Pointer to the last value read from the memory location.\r
+\r
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
+ @retval EFI_TIMEOUT Delay expired before a match occurred.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoPollMem (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ );\r
+\r
+/**\r
+ Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
+ satisfied or after a defined duration.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory operation.\r
+ @param Mask Mask used for the polling criteria.\r
+ @param Value The comparison value used for the polling exit criteria.\r
+ @param Delay The number of 100 ns units to poll.\r
+ @param Result Pointer to the last value read from the memory location.\r
+\r
+ @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
+ @retval EFI_TIMEOUT Delay expired before a match occurred.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoPollIo (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ );\r
+\r
+/**\r
+ Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
+ @param Count The number of memory or I/O operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI BAR specified by BarIndex.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoMemRead (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
+ @param Count The number of memory or I/O operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI BAR specified by BarIndex.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoMemWrite (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
+ @param Count The number of memory or I/O operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI BAR specified by BarIndex.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoIoRead (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory or I/O operations.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory or I/O operation to perform.\r
+ @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
+ @param Count The number of memory or I/O operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI BAR specified by BarIndex.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoIoWrite (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 BarIndex,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
+ @param Count The number of PCI configuration operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoConfigRead (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT32 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
+ @param Count The number of PCI configuration operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
+\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoConfigWrite (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT32 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
+ memory space.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
+ base address for the memory operation to perform.\r
+ @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
+ start the memory writes for the copy operation.\r
+ @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
+ base address for the memory operation to perform.\r
+ @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
+ the memory reads for the copy operation.\r
+ @param Count The number of memory operations to perform. Bytes moved is Width\r
+ size * Count, starting at DestOffset and SrcOffset.\r
+\r
+ @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
+ @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
+ is not valid for the PCI BAR specified by DestBarIndex.\r
+ @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
+ not valid for the PCI BAR specified by SrcBarIndex.\r
+ @retval EFI_INVALID_PARAMETER Width is invalid.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoCopyMem (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT8 DestBarIndex,\r
+ IN UINT64 DestOffset,\r
+ IN UINT8 SrcBarIndex,\r
+ IN UINT64 SrcOffset,\r
+ IN UINTN Count\r
+ );\r
+\r
+/**\r
+ Provides the PCI controller-specific addresses needed to access system memory.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Operation Indicates if the bus master is going to read or write to system memory.\r
+ @param HostAddress The system memory address to map to the PCI controller.\r
+ @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
+ that were mapped.\r
+ @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
+ access the hosts HostAddress.\r
+ @param Mapping A resulting value to pass to Unmap().\r
+\r
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoMap (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
+ IN VOID *HostAddress,\r
+ IN OUT UINTN *NumberOfBytes,\r
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
+ OUT VOID **Mapping\r
+ );\r
+\r
+/**\r
+ Completes the Map() operation and releases any corresponding resources.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Mapping The mapping value returned from Map().\r
+\r
+ @retval EFI_SUCCESS The range was unmapped.\r
+ @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoUnmap (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN VOID *Mapping\r
+ );\r
+\r
+/**\r
+ Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
+ mapping.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Type This parameter is not used and must be ignored.\r
+ @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
+ EfiRuntimeServicesData.\r
+ @param Pages The number of pages to allocate.\r
+ @param HostAddress A pointer to store the base system memory address of the\r
+ allocated range.\r
+ @param Attributes The requested bit mask of attributes for the allocated range.\r
+\r
+ @retval EFI_SUCCESS The requested memory pages were allocated.\r
+ @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
+ MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoAllocateBuffer (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN EFI_ALLOCATE_TYPE Type,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT VOID **HostAddress,\r
+ IN UINT64 Attributes\r
+ );\r
+\r
+/**\r
+ Frees memory that was allocated with AllocateBuffer().\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Pages The number of pages to free.\r
+ @param HostAddress The base system memory address of the allocated range.\r
+\r
+ @retval EFI_SUCCESS The requested memory pages were freed.\r
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
+ was not allocated with AllocateBuffer().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoFreeBuffer (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN UINTN Pages,\r
+ IN VOID *HostAddress\r
+ );\r
+\r
+/**\r
+ Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+\r
+ @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
+ bridge to system memory.\r
+ @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
+ host bridge due to a hardware error.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoFlush (\r
+ IN EFI_PCI_IO_PROTOCOL *This\r
+ );\r
+\r
+/**\r
+ Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param SegmentNumber The PCI controller's current PCI segment number.\r
+ @param BusNumber The PCI controller's current PCI bus number.\r
+ @param DeviceNumber The PCI controller's current PCI device number.\r
+ @param FunctionNumber The PCI controller's current PCI function number.\r
+\r
+ @retval EFI_SUCCESS The PCI controller location was returned.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoGetLocation (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ OUT UINTN *Segment,\r
+ OUT UINTN *Bus,\r
+ OUT UINTN *Device,\r
+ OUT UINTN *Function\r
+ );\r
+\r
+/**\r
+ Check BAR type for PCI resource.\r
+\r
+ @param PciIoDevice PCI device instance.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for the memory or I/O operation to perform.\r
+ @param BarType Memory or I/O.\r
+\r
+ @retval TRUE Pci device's bar type is same with input BarType.\r
+ @retval TRUE Pci device's bar type is not same with input BarType.\r
+\r
+**/\r
+BOOLEAN\r
+CheckBarType (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT8 BarIndex,\r
+ IN PCI_BAR_TYPE BarType\r
+ );\r
+\r
+/**\r
+ Set/Disable new attributes to a Root Bridge.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Attributes New attribute want to be set.\r
+ @param Operation Set or Disable.\r
+\r
+ @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
+ @retval EFI_SUCCESS Successfully set new attributs.\r
+\r
+**/\r
+EFI_STATUS\r
+ModifyRootBridgeAttributes (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN UINT64 Attributes,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
+ );\r
+\r
+/**\r
+ Check whether this device can be enable/disable to snoop.\r
+\r
+ @param PciIoDevice Pci device instance.\r
+ @param Operation Enable/Disable.\r
+\r
+ @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r
+ @retval EFI_SUCCESS Snoop can be supported.\r
+\r
+**/\r
+EFI_STATUS\r
+SupportPaletteSnoopAttributes (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
+ );\r
+\r
+/**\r
+ Performs an operation on the attributes that this PCI controller supports. The operations include\r
+ getting the set of supported attributes, retrieving the current attributes, setting the current\r
+ attributes, enabling attributes, and disabling attributes.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Operation The operation to perform on the attributes for this PCI controller.\r
+ @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
+ operations.\r
+ @param Result A pointer to the result mask of attributes that are returned for the Get\r
+ and Supported operations.\r
+\r
+ @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_UNSUPPORTED one or more of the bits set in\r
+ Attributes are not supported by this PCI controller or one of\r
+ its parent bridges when Operation is Set, Enable or Disable.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoAttributes (\r
+ IN EFI_PCI_IO_PROTOCOL * This,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
+ IN UINT64 Attributes,\r
+ OUT UINT64 *Result OPTIONAL\r
+ );\r
+\r
+/**\r
+ Gets the attributes that this PCI controller supports setting on a BAR using\r
+ SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for resource range. The legal range for this field is 0..5.\r
+ @param Supports A pointer to the mask of attributes that this PCI controller supports\r
+ setting for this BAR with SetBarAttributes().\r
+ @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
+ configuration of this BAR of the PCI controller.\r
+\r
+ @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
+ controller supports are returned in Supports. If Resources\r
+ is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
+ controller is currently using are returned in Resources.\r
+ @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
+ Resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoGetBarAttributes (\r
+ IN EFI_PCI_IO_PROTOCOL * This,\r
+ IN UINT8 BarIndex,\r
+ OUT UINT64 *Supports, OPTIONAL\r
+ OUT VOID **Resources OPTIONAL\r
+ );\r
+\r
+/**\r
+ Sets the attributes for a range of a BAR on a PCI controller.\r
+\r
+ @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Attributes The mask of attributes to set for the resource range specified by\r
+ BarIndex, Offset, and Length.\r
+ @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
+ base address for resource range. The legal range for this field is 0..5.\r
+ @param Offset A pointer to the BAR relative base address of the resource range to be\r
+ modified by the attributes specified by Attributes.\r
+ @param Length A pointer to the length of the resource range to be modified by the\r
+ attributes specified by Attributes.\r
+\r
+ @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
+ range specified by BarIndex, Offset, and Length were\r
+ set on the PCI controller, and the actual resource range is returned\r
+ in Offset and Length.\r
+ @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
+ @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
+ resource range specified by BarIndex, Offset, and\r
+ Length.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciIoSetBarAttributes (\r
+ IN EFI_PCI_IO_PROTOCOL *This,\r
+ IN UINT64 Attributes,\r
+ IN UINT8 BarIndex,\r
+ IN OUT UINT64 *Offset,\r
+ IN OUT UINT64 *Length\r
+ );\r
+\r
+/**\r
+ Program parent bridge's attribute recurrently.\r
+\r
+ @param PciIoDevice Child Pci device instance\r
+ @param Operation The operation to perform on the attributes for this PCI controller.\r
+ @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
+ operations.\r
+\r
+ @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+ @retval EFI_UNSUPPORTED one or more of the bits set in\r
+ Attributes are not supported by this PCI controller or one of\r
+ its parent bridges when Operation is Set, Enable or Disable.\r
+\r
+**/\r
+EFI_STATUS\r
+UpStreamBridgesAttributes (\r
+ IN PCI_IO_DEVICE *PciIoDevice,\r
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
+ IN UINT64 Attributes\r
+ );\r
+\r
+/**\r
+ Test whether two Pci devices has same parent bridge.\r
+\r
+ @param PciDevice1 The first pci device for testing.\r
+ @param PciDevice2 The second pci device for testing.\r
+\r
+ @retval TRUE Two Pci device has the same parent bridge.\r
+ @retval FALSE Two Pci device has not the same parent bridge.\r
+\r
+**/\r
+BOOLEAN\r
+PciDevicesOnTheSamePath (\r
+ IN PCI_IO_DEVICE *PciDevice1,\r
+ IN PCI_IO_DEVICE *PciDevice2\r
+ );\r
+\r
+#endif\r
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