clear the correct BAR register. Because for P2P device, only register from 0x10 to...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciOptionRomSupport.c

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
index 1db71fa8023e814c7695e1caa91098e0662f0934..5f8ffe2c05b245184115175991995a2f42e7e368 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI Rom supporting funtions implementation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -546,6 +546,7 @@ RomDecode (
 {\r
   UINT32              Value32;\r
   UINT32              Offset;\r
+  UINT32              OffsetMax;\r
   EFI_PCI_IO_PROTOCOL *PciIo;\r
 \r
   PciIo = &PciDevice->PciIo;\r
@@ -553,7 +554,12 @@ RomDecode (
     //\r
     // Clear all bars\r
     //\r
-    for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
+    OffsetMax = 0x24;\r
+    if (IS_PCI_BRIDGE(&PciDevice->Pci)) {\r
+      OffsetMax = 0x14;\r
+    }\r
+\r
+    for (Offset = 0x10; Offset <= OffsetMax; Offset += sizeof (UINT32)) {\r
       PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);\r
     }\r
 \r