#include "PciRootBridge.h"\r
#include "PciHostResource.h"\r
\r
-EFI_CPU_IO2_PROTOCOL *mCpuIo;\r
+EFI_CPU_IO2_PROTOCOL *mCpuIo;\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mAcpiAddressSpaceTypeStr[] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mAcpiAddressSpaceTypeStr[] = {\r
L"Mem", L"I/O", L"Bus"\r
};\r
-GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciResourceTypeStr[] = {\r
L"I/O", L"Mem", L"PMem", L"Mem64", L"PMem64", L"Bus"\r
};\r
\r
-EDKII_IOMMU_PROTOCOL *mIoMmu;\r
-EFI_EVENT mIoMmuEvent;\r
-VOID *mIoMmuRegistration;\r
+EDKII_IOMMU_PROTOCOL *mIoMmu;\r
+EFI_EVENT mIoMmuEvent;\r
+VOID *mIoMmuRegistration;\r
\r
/**\r
This routine gets translation offset from a root bridge instance by resource type.\r
**/\r
UINT64\r
GetTranslationByResourceType (\r
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,\r
- IN PCI_RESOURCE_TYPE ResourceType\r
+ IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge,\r
+ IN PCI_RESOURCE_TYPE ResourceType\r
)\r
{\r
switch (ResourceType) {\r
**/\r
EFI_STATUS\r
IntersectIoDescriptor (\r
- IN UINT64 Base,\r
- IN UINT64 Length,\r
- IN CONST EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor\r
+ IN UINT64 Base,\r
+ IN UINT64 Length,\r
+ IN CONST EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor\r
)\r
{\r
- UINT64 IntersectionBase;\r
- UINT64 IntersectionEnd;\r
- EFI_STATUS Status;\r
+ UINT64 IntersectionBase;\r
+ UINT64 IntersectionEnd;\r
+ EFI_STATUS Status;\r
\r
if (Descriptor->GcdIoType == EfiGcdIoTypeIo) {\r
return EFI_SUCCESS;\r
}\r
\r
IntersectionBase = MAX (Base, Descriptor->BaseAddress);\r
- IntersectionEnd = MIN (Base + Length,\r
- Descriptor->BaseAddress + Descriptor->Length);\r
+ IntersectionEnd = MIN (\r
+ Base + Length,\r
+ Descriptor->BaseAddress + Descriptor->Length\r
+ );\r
if (IntersectionBase >= IntersectionEnd) {\r
//\r
// The descriptor and the aperture don't overlap.\r
}\r
\r
if (Descriptor->GcdIoType == EfiGcdIoTypeNonExistent) {\r
- Status = gDS->AddIoSpace (EfiGcdIoTypeIo, IntersectionBase,\r
- IntersectionEnd - IntersectionBase);\r
+ Status = gDS->AddIoSpace (\r
+ EfiGcdIoTypeIo,\r
+ IntersectionBase,\r
+ IntersectionEnd - IntersectionBase\r
+ );\r
\r
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
- "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,\r
- IntersectionBase, IntersectionEnd, Status));\r
+ DEBUG ((\r
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
+ "%a: %a: add [%Lx, %Lx): %r\n",\r
+ gEfiCallerBaseName,\r
+ __FUNCTION__,\r
+ IntersectionBase,\r
+ IntersectionEnd,\r
+ Status\r
+ ));\r
return Status;\r
}\r
\r
- DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u conflicts with "\r
- "aperture [%Lx, %Lx)\n", gEfiCallerBaseName, __FUNCTION__,\r
- Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,\r
- (UINT32)Descriptor->GcdIoType, Base, Base + Length));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %a: desc [%Lx, %Lx) type %u conflicts with "\r
+ "aperture [%Lx, %Lx)\n",\r
+ gEfiCallerBaseName,\r
+ __FUNCTION__,\r
+ Descriptor->BaseAddress,\r
+ Descriptor->BaseAddress + Descriptor->Length,\r
+ (UINT32)Descriptor->GcdIoType,\r
+ Base,\r
+ Base + Length\r
+ ));\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
**/\r
EFI_STATUS\r
AddIoSpace (\r
- IN UINT64 Base,\r
- IN UINT64 Length\r
+ IN UINT64 Base,\r
+ IN UINT64 Length\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINTN NumberOfDescriptors;\r
- EFI_GCD_IO_SPACE_DESCRIPTOR *IoSpaceMap;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN NumberOfDescriptors;\r
+ EFI_GCD_IO_SPACE_DESCRIPTOR *IoSpaceMap;\r
\r
Status = gDS->GetIoSpaceMap (&NumberOfDescriptors, &IoSpaceMap);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: %a: GetIoSpaceMap(): %r\n",\r
- gEfiCallerBaseName, __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %a: GetIoSpaceMap(): %r\n",\r
+ gEfiCallerBaseName,\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
return Status;\r
}\r
\r
}\r
}\r
\r
- DEBUG_CODE_BEGIN ();\r
- //\r
- // Make sure there are adjacent descriptors covering [Base, Base + Length).\r
- // It is possible that they have not been merged; merging can be prevented\r
- // by allocation.\r
- //\r
- UINT64 CheckBase;\r
- EFI_STATUS CheckStatus;\r
- EFI_GCD_IO_SPACE_DESCRIPTOR Descriptor;\r
-\r
- for (CheckBase = Base;\r
- CheckBase < Base + Length;\r
- CheckBase = Descriptor.BaseAddress + Descriptor.Length) {\r
- CheckStatus = gDS->GetIoSpaceDescriptor (CheckBase, &Descriptor);\r
- ASSERT_EFI_ERROR (CheckStatus);\r
- ASSERT (Descriptor.GcdIoType == EfiGcdIoTypeIo);\r
- }\r
- DEBUG_CODE_END ();\r
+ DEBUG_CODE_BEGIN ();\r
+ //\r
+ // Make sure there are adjacent descriptors covering [Base, Base + Length).\r
+ // It is possible that they have not been merged; merging can be prevented\r
+ // by allocation.\r
+ //\r
+ UINT64 CheckBase;\r
+ EFI_STATUS CheckStatus;\r
+ EFI_GCD_IO_SPACE_DESCRIPTOR Descriptor;\r
+\r
+ for (CheckBase = Base;\r
+ CheckBase < Base + Length;\r
+ CheckBase = Descriptor.BaseAddress + Descriptor.Length)\r
+ {\r
+ CheckStatus = gDS->GetIoSpaceDescriptor (CheckBase, &Descriptor);\r
+ ASSERT_EFI_ERROR (CheckStatus);\r
+ ASSERT (Descriptor.GcdIoType == EfiGcdIoTypeIo);\r
+ }\r
+\r
+ DEBUG_CODE_END ();\r
\r
FreeIoSpaceMap:\r
FreePool (IoSpaceMap);\r
**/\r
EFI_STATUS\r
IntersectMemoryDescriptor (\r
- IN UINT64 Base,\r
- IN UINT64 Length,\r
- IN UINT64 Capabilities,\r
- IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor\r
+ IN UINT64 Base,\r
+ IN UINT64 Length,\r
+ IN UINT64 Capabilities,\r
+ IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor\r
)\r
{\r
- UINT64 IntersectionBase;\r
- UINT64 IntersectionEnd;\r
- EFI_STATUS Status;\r
+ UINT64 IntersectionBase;\r
+ UINT64 IntersectionEnd;\r
+ EFI_STATUS Status;\r
\r
- if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&\r
- (Descriptor->Capabilities & Capabilities) == Capabilities) {\r
+ if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&\r
+ ((Descriptor->Capabilities & Capabilities) == Capabilities))\r
+ {\r
return EFI_SUCCESS;\r
}\r
\r
IntersectionBase = MAX (Base, Descriptor->BaseAddress);\r
- IntersectionEnd = MIN (Base + Length,\r
- Descriptor->BaseAddress + Descriptor->Length);\r
+ IntersectionEnd = MIN (\r
+ Base + Length,\r
+ Descriptor->BaseAddress + Descriptor->Length\r
+ );\r
if (IntersectionBase >= IntersectionEnd) {\r
//\r
// The descriptor and the aperture don't overlap.\r
}\r
\r
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
- Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,\r
- IntersectionBase, IntersectionEnd - IntersectionBase,\r
- Capabilities);\r
+ Status = gDS->AddMemorySpace (\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ IntersectionBase,\r
+ IntersectionEnd - IntersectionBase,\r
+ Capabilities\r
+ );\r
\r
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
- "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,\r
- IntersectionBase, IntersectionEnd, Status));\r
+ DEBUG ((\r
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
+ "%a: %a: add [%Lx, %Lx): %r\n",\r
+ gEfiCallerBaseName,\r
+ __FUNCTION__,\r
+ IntersectionBase,\r
+ IntersectionEnd,\r
+ Status\r
+ ));\r
return Status;\r
}\r
\r
- DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r
- "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,\r
- Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,\r
- (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,\r
- Base, Base + Length, Capabilities));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r
+ "with aperture [%Lx, %Lx) cap %Lx\n",\r
+ gEfiCallerBaseName,\r
+ __FUNCTION__,\r
+ Descriptor->BaseAddress,\r
+ Descriptor->BaseAddress + Descriptor->Length,\r
+ (UINT32)Descriptor->GcdMemoryType,\r
+ Descriptor->Capabilities,\r
+ Base,\r
+ Base + Length,\r
+ Capabilities\r
+ ));\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
**/\r
EFI_STATUS\r
AddMemoryMappedIoSpace (\r
- IN UINT64 Base,\r
- IN UINT64 Length,\r
- IN UINT64 Capabilities\r
+ IN UINT64 Base,\r
+ IN UINT64 Length,\r
+ IN UINT64 Capabilities\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINTN NumberOfDescriptors;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN NumberOfDescriptors;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
\r
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",\r
- gEfiCallerBaseName, __FUNCTION__, Status));\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: %a: GetMemorySpaceMap(): %r\n",\r
+ gEfiCallerBaseName,\r
+ __FUNCTION__,\r
+ Status\r
+ ));\r
return Status;\r
}\r
\r
for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
- Status = IntersectMemoryDescriptor (Base, Length, Capabilities,\r
- &MemorySpaceMap[Index]);\r
+ Status = IntersectMemoryDescriptor (\r
+ Base,\r
+ Length,\r
+ Capabilities,\r
+ &MemorySpaceMap[Index]\r
+ );\r
if (EFI_ERROR (Status)) {\r
goto FreeMemorySpaceMap;\r
}\r
}\r
\r
DEBUG_CODE_BEGIN ();\r
- //\r
- // Make sure there are adjacent descriptors covering [Base, Base + Length).\r
- // It is possible that they have not been merged; merging can be prevented\r
- // by allocation and different capabilities.\r
- //\r
- UINT64 CheckBase;\r
- EFI_STATUS CheckStatus;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r
-\r
- for (CheckBase = Base;\r
- CheckBase < Base + Length;\r
- CheckBase = Descriptor.BaseAddress + Descriptor.Length) {\r
- CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);\r
- ASSERT_EFI_ERROR (CheckStatus);\r
- ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);\r
- ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);\r
- }\r
+ //\r
+ // Make sure there are adjacent descriptors covering [Base, Base + Length).\r
+ // It is possible that they have not been merged; merging can be prevented\r
+ // by allocation and different capabilities.\r
+ //\r
+ UINT64 CheckBase;\r
+ EFI_STATUS CheckStatus;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r
+\r
+ for (CheckBase = Base;\r
+ CheckBase < Base + Length;\r
+ CheckBase = Descriptor.BaseAddress + Descriptor.Length)\r
+ {\r
+ CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);\r
+ ASSERT_EFI_ERROR (CheckStatus);\r
+ ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);\r
+ ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);\r
+ }\r
+\r
DEBUG_CODE_END ();\r
\r
FreeMemorySpaceMap:\r
VOID\r
EFIAPI\r
IoMmuProtocolCallback (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu);\r
- if (!EFI_ERROR(Status)) {\r
+ if (!EFI_ERROR (Status)) {\r
gBS->CloseEvent (mIoMmuEvent);\r
}\r
}\r
EFI_STATUS\r
EFIAPI\r
InitializePciHostBridge (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- PCI_ROOT_BRIDGE *RootBridges;\r
- UINTN RootBridgeCount;\r
- UINTN Index;\r
- PCI_ROOT_BRIDGE_APERTURE *MemApertures[4];\r
- UINTN MemApertureIndex;\r
- BOOLEAN ResourceAssigned;\r
- LIST_ENTRY *Link;\r
- UINT64 HostAddress;\r
+ EFI_STATUS Status;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
+ PCI_ROOT_BRIDGE *RootBridges;\r
+ UINTN RootBridgeCount;\r
+ UINTN Index;\r
+ PCI_ROOT_BRIDGE_APERTURE *MemApertures[4];\r
+ UINTN MemApertureIndex;\r
+ BOOLEAN ResourceAssigned;\r
+ LIST_ENTRY *Link;\r
+ UINT64 HostAddress;\r
\r
RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount);\r
if ((RootBridges == NULL) || (RootBridgeCount == 0)) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
- Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) &mCpuIo);\r
+ Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&mCpuIo);\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
HostBridge = AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE));\r
ASSERT (HostBridge != NULL);\r
\r
- HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;\r
- HostBridge->CanRestarted = TRUE;\r
+ HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;\r
+ HostBridge->CanRestarted = TRUE;\r
InitializeListHead (&HostBridge->RootBridges);\r
- ResourceAssigned = FALSE;\r
+ ResourceAssigned = FALSE;\r
\r
//\r
// Create Root Bridge Device Handle in this Host Bridge\r
// Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.\r
// For GCD resource manipulation, we need to use host address.\r
//\r
- HostAddress = TO_HOST_ADDRESS (RootBridges[Index].Io.Base,\r
- RootBridges[Index].Io.Translation);\r
+ HostAddress = TO_HOST_ADDRESS (\r
+ RootBridges[Index].Io.Base,\r
+ RootBridges[Index].Io.Translation\r
+ );\r
\r
Status = AddIoSpace (\r
HostAddress,\r
// Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.\r
// For GCD resource manipulation, we need to use host address.\r
//\r
- HostAddress = TO_HOST_ADDRESS (MemApertures[MemApertureIndex]->Base,\r
- MemApertures[MemApertureIndex]->Translation);\r
+ HostAddress = TO_HOST_ADDRESS (\r
+ MemApertures[MemApertureIndex]->Base,\r
+ MemApertures[MemApertureIndex]->Translation\r
+ );\r
Status = AddMemoryMappedIoSpace (\r
HostAddress,\r
MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set EFI_MEMORY_UC to MMIO aperture - %r.\n", Status));\r
}\r
+\r
if (ResourceAssigned) {\r
Status = gDS->AllocateMemorySpace (\r
EfiGcdAllocateAddress,\r
}\r
}\r
}\r
+\r
//\r
// Insert Root Bridge Handle Instance\r
//\r
// PciHostBridgeResourceAllocation protocol.\r
//\r
if (!ResourceAssigned) {\r
- HostBridge->ResAlloc.NotifyPhase = NotifyPhase;\r
- HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;\r
- HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;\r
- HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;\r
- HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;\r
- HostBridge->ResAlloc.SubmitResources = SubmitResources;\r
+ HostBridge->ResAlloc.NotifyPhase = NotifyPhase;\r
+ HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;\r
+ HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;\r
+ HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;\r
+ HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;\r
+ HostBridge->ResAlloc.SubmitResources = SubmitResources;\r
HostBridge->ResAlloc.GetProposedResources = GetProposedResources;\r
HostBridge->ResAlloc.PreprocessController = PreprocessController;\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&HostBridge->Handle,\r
- &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,\r
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
+ &HostBridge->ResAlloc,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
; !IsNull (&HostBridge->RootBridges, Link)\r
; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
+ )\r
+ {\r
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
RootBridge->RootBridgeIo.ParentHandle = HostBridge->Handle;\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&RootBridge->Handle,\r
- &gEfiDevicePathProtocolGuid, RootBridge->DevicePath,\r
- &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->RootBridgeIo,\r
+ &gEfiDevicePathProtocolGuid,\r
+ RootBridge->DevicePath,\r
+ &gEfiPciRootBridgeIoProtocolGuid,\r
+ &RootBridge->RootBridgeIo,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
}\r
+\r
PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);\r
\r
if (!EFI_ERROR (Status)) {\r
**/\r
VOID\r
ResourceConflict (\r
- IN PCI_HOST_BRIDGE_INSTANCE *HostBridge\r
+ IN PCI_HOST_BRIDGE_INSTANCE *HostBridge\r
)\r
{\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
- EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- LIST_ENTRY *Link;\r
- UINTN RootBridgeCount;\r
- PCI_RESOURCE_TYPE Index;\r
- PCI_RES_NODE *ResAllocNode;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
+ LIST_ENTRY *Link;\r
+ UINTN RootBridgeCount;\r
+ PCI_RESOURCE_TYPE Index;\r
+ PCI_RES_NODE *ResAllocNode;\r
\r
RootBridgeCount = 0;\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
; !IsNull (&HostBridge->RootBridges, Link)\r
; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ )\r
+ {\r
RootBridgeCount++;\r
}\r
\r
for (Link = GetFirstNode (&HostBridge->RootBridges), Descriptor = Resources\r
; !IsNull (&HostBridge->RootBridges, Link)\r
; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
for (Index = TypeIo; Index < TypeMax; Index++) {\r
ResAllocNode = &RootBridge->ResAllocNode[Index];\r
\r
- Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
Descriptor->AddrRangeMin = ResAllocNode->Base;\r
Descriptor->AddrRangeMax = ResAllocNode->Alignment;\r
Descriptor->AddrLen = ResAllocNode->Length;\r
Descriptor->SpecificFlag = 0;\r
switch (ResAllocNode->Type) {\r
+ case TypeIo:\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
+ break;\r
+\r
+ case TypePMem32:\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
+ case TypeMem32:\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->AddrSpaceGranularity = 32;\r
+ break;\r
+\r
+ case TypePMem64:\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
+ case TypeMem64:\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->AddrSpaceGranularity = 64;\r
+ break;\r
+\r
+ case TypeBus:\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
+ break;\r
\r
- case TypeIo:\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
- break;\r
-\r
- case TypePMem32:\r
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
- case TypeMem32:\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Descriptor->AddrSpaceGranularity = 32;\r
- break;\r
-\r
- case TypePMem64:\r
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
- case TypeMem64:\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Descriptor->AddrSpaceGranularity = 64;\r
- break;\r
-\r
- case TypeBus:\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
- break;\r
-\r
- default:\r
- break;\r
+ default:\r
+ break;\r
}\r
\r
Descriptor++;\r
}\r
+\r
//\r
// Terminate the root bridge resources.\r
//\r
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;\r
- End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;\r
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
End->Checksum = 0x0;\r
\r
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (End + 1);\r
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(End + 1);\r
}\r
+\r
//\r
// Terminate the host bridge resources.\r
//\r
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;\r
- End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;\r
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
End->Checksum = 0x0;\r
\r
DEBUG ((DEBUG_ERROR, "Call PciHostBridgeResourceConflict().\n"));\r
**/\r
UINT64\r
AllocateResource (\r
- BOOLEAN Mmio,\r
- UINT64 Length,\r
- UINTN BitsOfAlignment,\r
- UINT64 BaseAddress,\r
- UINT64 Limit\r
+ BOOLEAN Mmio,\r
+ UINT64 Length,\r
+ UINTN BitsOfAlignment,\r
+ UINT64 BaseAddress,\r
+ UINT64 Limit\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (BaseAddress < Limit) {\r
//\r
if (!EFI_ERROR (Status)) {\r
return BaseAddress;\r
}\r
+\r
BaseAddress += LShiftU64 (1, BitsOfAlignment);\r
}\r
}\r
+\r
return MAX_UINT64;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
NotifyPhase (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
)\r
{\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- LIST_ENTRY *Link;\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
- UINTN BitsOfAlignment;\r
- UINT64 Alignment;\r
- EFI_STATUS Status;\r
- EFI_STATUS ReturnStatus;\r
- PCI_RESOURCE_TYPE Index;\r
- PCI_RESOURCE_TYPE Index1;\r
- PCI_RESOURCE_TYPE Index2;\r
- BOOLEAN ResNodeHandled[TypeMax];\r
- UINT64 MaxAlignment;\r
- UINT64 Translation;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
+ LIST_ENTRY *Link;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ UINTN BitsOfAlignment;\r
+ UINT64 Alignment;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS ReturnStatus;\r
+ PCI_RESOURCE_TYPE Index;\r
+ PCI_RESOURCE_TYPE Index1;\r
+ PCI_RESOURCE_TYPE Index2;\r
+ BOOLEAN ResNodeHandled[TypeMax];\r
+ UINT64 MaxAlignment;\r
+ UINT64 Translation;\r
\r
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);\r
\r
switch (Phase) {\r
- case EfiPciHostBridgeBeginEnumeration:\r
- if (!HostBridge->CanRestarted) {\r
- return EFI_NOT_READY;\r
- }\r
- //\r
- // Reset Root Bridge\r
- //\r
- for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
- for (Index = TypeIo; Index < TypeMax; Index++) {\r
- RootBridge->ResAllocNode[Index].Type = Index;\r
- RootBridge->ResAllocNode[Index].Base = 0;\r
- RootBridge->ResAllocNode[Index].Length = 0;\r
- RootBridge->ResAllocNode[Index].Status = ResNone;\r
-\r
- RootBridge->ResourceSubmitted = FALSE;\r
+ case EfiPciHostBridgeBeginEnumeration:\r
+ if (!HostBridge->CanRestarted) {\r
+ return EFI_NOT_READY;\r
}\r
- }\r
\r
- HostBridge->CanRestarted = TRUE;\r
- break;\r
+ //\r
+ // Reset Root Bridge\r
+ //\r
+ for (Link = GetFirstNode (&HostBridge->RootBridges)\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
+ for (Index = TypeIo; Index < TypeMax; Index++) {\r
+ RootBridge->ResAllocNode[Index].Type = Index;\r
+ RootBridge->ResAllocNode[Index].Base = 0;\r
+ RootBridge->ResAllocNode[Index].Length = 0;\r
+ RootBridge->ResAllocNode[Index].Status = ResNone;\r
+\r
+ RootBridge->ResourceSubmitted = FALSE;\r
+ }\r
+ }\r
\r
- case EfiPciHostBridgeBeginBusAllocation:\r
- //\r
- // No specific action is required here, can perform any chipset specific programing\r
- //\r
- HostBridge->CanRestarted = FALSE;\r
- break;\r
+ HostBridge->CanRestarted = TRUE;\r
+ break;\r
\r
- case EfiPciHostBridgeEndBusAllocation:\r
- //\r
- // No specific action is required here, can perform any chipset specific programing\r
- //\r
- break;\r
+ case EfiPciHostBridgeBeginBusAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ HostBridge->CanRestarted = FALSE;\r
+ break;\r
\r
- case EfiPciHostBridgeBeginResourceAllocation:\r
- //\r
- // No specific action is required here, can perform any chipset specific programing\r
- //\r
- break;\r
+ case EfiPciHostBridgeEndBusAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ break;\r
\r
- case EfiPciHostBridgeAllocateResources:\r
- ReturnStatus = EFI_SUCCESS;\r
+ case EfiPciHostBridgeBeginResourceAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ break;\r
\r
- //\r
- // Make sure the resource for all root bridges has been submitted.\r
- //\r
- for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
- if (!RootBridge->ResourceSubmitted) {\r
- return EFI_NOT_READY;\r
- }\r
- }\r
+ case EfiPciHostBridgeAllocateResources:\r
+ ReturnStatus = EFI_SUCCESS;\r
\r
- DEBUG ((DEBUG_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));\r
- for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
- for (Index = TypeIo; Index < TypeBus; Index++) {\r
- ResNodeHandled[Index] = FALSE;\r
+ //\r
+ // Make sure the resource for all root bridges has been submitted.\r
+ //\r
+ for (Link = GetFirstNode (&HostBridge->RootBridges)\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
+ if (!RootBridge->ResourceSubmitted) {\r
+ return EFI_NOT_READY;\r
+ }\r
}\r
\r
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
- DEBUG ((DEBUG_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));\r
-\r
- for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {\r
- if (RootBridge->ResAllocNode[Index1].Status == ResNone) {\r
- ResNodeHandled[Index1] = TRUE;\r
- } else {\r
- //\r
- // Allocate the resource node with max alignment at first\r
- //\r
- MaxAlignment = 0;\r
- Index = TypeMax;\r
- for (Index2 = TypeIo; Index2 < TypeBus; Index2++) {\r
- if (ResNodeHandled[Index2]) {\r
- continue;\r
- }\r
- if (MaxAlignment <= RootBridge->ResAllocNode[Index2].Alignment) {\r
- MaxAlignment = RootBridge->ResAllocNode[Index2].Alignment;\r
- Index = Index2;\r
- }\r
- }\r
+ DEBUG ((DEBUG_INFO, "PciHostBridge: NotifyPhase (AllocateResources)\n"));\r
+ for (Link = GetFirstNode (&HostBridge->RootBridges)\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
+ for (Index = TypeIo; Index < TypeBus; Index++) {\r
+ ResNodeHandled[Index] = FALSE;\r
+ }\r
\r
- ASSERT (Index < TypeMax);\r
- ResNodeHandled[Index] = TRUE;\r
- Alignment = RootBridge->ResAllocNode[Index].Alignment;\r
- BitsOfAlignment = LowBitSet64 (Alignment + 1);\r
- BaseAddress = MAX_UINT64;\r
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
+ DEBUG ((DEBUG_INFO, " RootBridge: %s\n", RootBridge->DevicePathStr));\r
\r
- //\r
- // RESTRICTION: To simplify the situation, we require the alignment of\r
- // Translation must be larger than any BAR alignment in the same root\r
- // bridge, so that resource allocation alignment can be applied to\r
- // both device address and host address.\r
- //\r
- Translation = GetTranslationByResourceType (RootBridge, Index);\r
- if ((Translation & Alignment) != 0) {\r
- DEBUG ((DEBUG_ERROR, "[%a:%d] Translation %lx is not aligned to %lx!\n",\r
- __FUNCTION__, DEBUG_LINE_NUMBER, Translation, Alignment\r
- ));\r
- ASSERT ((Translation & Alignment) == 0);\r
+ for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {\r
+ if (RootBridge->ResAllocNode[Index1].Status == ResNone) {\r
+ ResNodeHandled[Index1] = TRUE;\r
+ } else {\r
//\r
- // This may be caused by too large alignment or too small\r
- // Translation; pick the 1st possibility and return out of resource,\r
- // which can also go thru the same process for out of resource\r
- // outside the loop.\r
+ // Allocate the resource node with max alignment at first\r
//\r
- ReturnStatus = EFI_OUT_OF_RESOURCES;\r
- continue;\r
- }\r
+ MaxAlignment = 0;\r
+ Index = TypeMax;\r
+ for (Index2 = TypeIo; Index2 < TypeBus; Index2++) {\r
+ if (ResNodeHandled[Index2]) {\r
+ continue;\r
+ }\r
+\r
+ if (MaxAlignment <= RootBridge->ResAllocNode[Index2].Alignment) {\r
+ MaxAlignment = RootBridge->ResAllocNode[Index2].Alignment;\r
+ Index = Index2;\r
+ }\r
+ }\r
\r
- switch (Index) {\r
- case TypeIo:\r
- //\r
- // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.\r
- // For AllocateResource is manipulating GCD resource, we need to use\r
- // host address here.\r
- //\r
- BaseAddress = AllocateResource (\r
- FALSE,\r
- RootBridge->ResAllocNode[Index].Length,\r
- MIN (15, BitsOfAlignment),\r
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),\r
- RootBridge->Io.Translation),\r
- TO_HOST_ADDRESS (RootBridge->Io.Limit,\r
- RootBridge->Io.Translation)\r
- );\r
- break;\r
+ ASSERT (Index < TypeMax);\r
+ ResNodeHandled[Index] = TRUE;\r
+ Alignment = RootBridge->ResAllocNode[Index].Alignment;\r
+ BitsOfAlignment = LowBitSet64 (Alignment + 1);\r
+ BaseAddress = MAX_UINT64;\r
\r
- case TypeMem64:\r
- BaseAddress = AllocateResource (\r
- TRUE,\r
- RootBridge->ResAllocNode[Index].Length,\r
- MIN (63, BitsOfAlignment),\r
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),\r
- RootBridge->MemAbove4G.Translation),\r
- TO_HOST_ADDRESS (RootBridge->MemAbove4G.Limit,\r
- RootBridge->MemAbove4G.Translation)\r
- );\r
- if (BaseAddress != MAX_UINT64) {\r
- break;\r
- }\r
//\r
- // If memory above 4GB is not available, try memory below 4GB\r
+ // RESTRICTION: To simplify the situation, we require the alignment of\r
+ // Translation must be larger than any BAR alignment in the same root\r
+ // bridge, so that resource allocation alignment can be applied to\r
+ // both device address and host address.\r
//\r
+ Translation = GetTranslationByResourceType (RootBridge, Index);\r
+ if ((Translation & Alignment) != 0) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "[%a:%d] Translation %lx is not aligned to %lx!\n",\r
+ __FUNCTION__,\r
+ DEBUG_LINE_NUMBER,\r
+ Translation,\r
+ Alignment\r
+ ));\r
+ ASSERT ((Translation & Alignment) == 0);\r
+ //\r
+ // This may be caused by too large alignment or too small\r
+ // Translation; pick the 1st possibility and return out of resource,\r
+ // which can also go thru the same process for out of resource\r
+ // outside the loop.\r
+ //\r
+ ReturnStatus = EFI_OUT_OF_RESOURCES;\r
+ continue;\r
+ }\r
\r
- case TypeMem32:\r
- BaseAddress = AllocateResource (\r
- TRUE,\r
- RootBridge->ResAllocNode[Index].Length,\r
- MIN (31, BitsOfAlignment),\r
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),\r
- RootBridge->Mem.Translation),\r
- TO_HOST_ADDRESS (RootBridge->Mem.Limit,\r
- RootBridge->Mem.Translation)\r
- );\r
- break;\r
+ switch (Index) {\r
+ case TypeIo:\r
+ //\r
+ // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.\r
+ // For AllocateResource is manipulating GCD resource, we need to use\r
+ // host address here.\r
+ //\r
+ BaseAddress = AllocateResource (\r
+ FALSE,\r
+ RootBridge->ResAllocNode[Index].Length,\r
+ MIN (15, BitsOfAlignment),\r
+ TO_HOST_ADDRESS (\r
+ ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1),\r
+ RootBridge->Io.Translation\r
+ ),\r
+ TO_HOST_ADDRESS (\r
+ RootBridge->Io.Limit,\r
+ RootBridge->Io.Translation\r
+ )\r
+ );\r
+ break;\r
+\r
+ case TypeMem64:\r
+ BaseAddress = AllocateResource (\r
+ TRUE,\r
+ RootBridge->ResAllocNode[Index].Length,\r
+ MIN (63, BitsOfAlignment),\r
+ TO_HOST_ADDRESS (\r
+ ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1),\r
+ RootBridge->MemAbove4G.Translation\r
+ ),\r
+ TO_HOST_ADDRESS (\r
+ RootBridge->MemAbove4G.Limit,\r
+ RootBridge->MemAbove4G.Translation\r
+ )\r
+ );\r
+ if (BaseAddress != MAX_UINT64) {\r
+ break;\r
+ }\r
+\r
+ //\r
+ // If memory above 4GB is not available, try memory below 4GB\r
+ //\r
+\r
+ case TypeMem32:\r
+ BaseAddress = AllocateResource (\r
+ TRUE,\r
+ RootBridge->ResAllocNode[Index].Length,\r
+ MIN (31, BitsOfAlignment),\r
+ TO_HOST_ADDRESS (\r
+ ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1),\r
+ RootBridge->Mem.Translation\r
+ ),\r
+ TO_HOST_ADDRESS (\r
+ RootBridge->Mem.Limit,\r
+ RootBridge->Mem.Translation\r
+ )\r
+ );\r
+ break;\r
+\r
+ case TypePMem64:\r
+ BaseAddress = AllocateResource (\r
+ TRUE,\r
+ RootBridge->ResAllocNode[Index].Length,\r
+ MIN (63, BitsOfAlignment),\r
+ TO_HOST_ADDRESS (\r
+ ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),\r
+ RootBridge->PMemAbove4G.Translation\r
+ ),\r
+ TO_HOST_ADDRESS (\r
+ RootBridge->PMemAbove4G.Limit,\r
+ RootBridge->PMemAbove4G.Translation\r
+ )\r
+ );\r
+ if (BaseAddress != MAX_UINT64) {\r
+ break;\r
+ }\r
+\r
+ //\r
+ // If memory above 4GB is not available, try memory below 4GB\r
+ //\r
+ case TypePMem32:\r
+ BaseAddress = AllocateResource (\r
+ TRUE,\r
+ RootBridge->ResAllocNode[Index].Length,\r
+ MIN (31, BitsOfAlignment),\r
+ TO_HOST_ADDRESS (\r
+ ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),\r
+ RootBridge->PMem.Translation\r
+ ),\r
+ TO_HOST_ADDRESS (\r
+ RootBridge->PMem.Limit,\r
+ RootBridge->PMem.Translation\r
+ )\r
+ );\r
+ break;\r
+\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
\r
- case TypePMem64:\r
- BaseAddress = AllocateResource (\r
- TRUE,\r
- RootBridge->ResAllocNode[Index].Length,\r
- MIN (63, BitsOfAlignment),\r
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1),\r
- RootBridge->PMemAbove4G.Translation),\r
- TO_HOST_ADDRESS (RootBridge->PMemAbove4G.Limit,\r
- RootBridge->PMemAbove4G.Translation)\r
- );\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ " %s: Base/Length/Alignment = %lx/%lx/%lx - ",\r
+ mPciResourceTypeStr[Index],\r
+ BaseAddress,\r
+ RootBridge->ResAllocNode[Index].Length,\r
+ Alignment\r
+ ));\r
if (BaseAddress != MAX_UINT64) {\r
- break;\r
+ RootBridge->ResAllocNode[Index].Base = BaseAddress;\r
+ RootBridge->ResAllocNode[Index].Status = ResAllocated;\r
+ DEBUG ((DEBUG_INFO, "Success\n"));\r
+ } else {\r
+ ReturnStatus = EFI_OUT_OF_RESOURCES;\r
+ DEBUG ((DEBUG_ERROR, "Out Of Resource!\n"));\r
}\r
- //\r
- // If memory above 4GB is not available, try memory below 4GB\r
- //\r
- case TypePMem32:\r
- BaseAddress = AllocateResource (\r
- TRUE,\r
- RootBridge->ResAllocNode[Index].Length,\r
- MIN (31, BitsOfAlignment),\r
- TO_HOST_ADDRESS (ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1),\r
- RootBridge->PMem.Translation),\r
- TO_HOST_ADDRESS (RootBridge->PMem.Limit,\r
- RootBridge->PMem.Translation)\r
- );\r
- break;\r
-\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
- }\r
-\r
- DEBUG ((DEBUG_INFO, " %s: Base/Length/Alignment = %lx/%lx/%lx - ",\r
- mPciResourceTypeStr[Index], BaseAddress, RootBridge->ResAllocNode[Index].Length, Alignment));\r
- if (BaseAddress != MAX_UINT64) {\r
- RootBridge->ResAllocNode[Index].Base = BaseAddress;\r
- RootBridge->ResAllocNode[Index].Status = ResAllocated;\r
- DEBUG ((DEBUG_INFO, "Success\n"));\r
- } else {\r
- ReturnStatus = EFI_OUT_OF_RESOURCES;\r
- DEBUG ((DEBUG_ERROR, "Out Of Resource!\n"));\r
}\r
}\r
}\r
- }\r
\r
- if (ReturnStatus == EFI_OUT_OF_RESOURCES) {\r
- ResourceConflict (HostBridge);\r
- }\r
+ if (ReturnStatus == EFI_OUT_OF_RESOURCES) {\r
+ ResourceConflict (HostBridge);\r
+ }\r
\r
- //\r
- // Set resource to zero for nodes where allocation fails\r
- //\r
- for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
- for (Index = TypeIo; Index < TypeBus; Index++) {\r
- if (RootBridge->ResAllocNode[Index].Status != ResAllocated) {\r
- RootBridge->ResAllocNode[Index].Length = 0;\r
+ //\r
+ // Set resource to zero for nodes where allocation fails\r
+ //\r
+ for (Link = GetFirstNode (&HostBridge->RootBridges)\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
+ for (Index = TypeIo; Index < TypeBus; Index++) {\r
+ if (RootBridge->ResAllocNode[Index].Status != ResAllocated) {\r
+ RootBridge->ResAllocNode[Index].Length = 0;\r
+ }\r
}\r
}\r
- }\r
- return ReturnStatus;\r
\r
- case EfiPciHostBridgeSetResources:\r
- //\r
- // HostBridgeInstance->CanRestarted = FALSE;\r
- //\r
- break;\r
+ return ReturnStatus;\r
\r
- case EfiPciHostBridgeFreeResources:\r
- //\r
- // HostBridgeInstance->CanRestarted = FALSE;\r
- //\r
- ReturnStatus = EFI_SUCCESS;\r
- for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
- RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
- for (Index = TypeIo; Index < TypeBus; Index++) {\r
- if (RootBridge->ResAllocNode[Index].Status == ResAllocated) {\r
- switch (Index) {\r
- case TypeIo:\r
- Status = gDS->FreeIoSpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);\r
- if (EFI_ERROR (Status)) {\r
- ReturnStatus = Status;\r
- }\r
- break;\r
+ case EfiPciHostBridgeSetResources:\r
+ //\r
+ // HostBridgeInstance->CanRestarted = FALSE;\r
+ //\r
+ break;\r
\r
- case TypeMem32:\r
- case TypePMem32:\r
- case TypeMem64:\r
- case TypePMem64:\r
- Status = gDS->FreeMemorySpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);\r
- if (EFI_ERROR (Status)) {\r
- ReturnStatus = Status;\r
+ case EfiPciHostBridgeFreeResources:\r
+ //\r
+ // HostBridgeInstance->CanRestarted = FALSE;\r
+ //\r
+ ReturnStatus = EFI_SUCCESS;\r
+ for (Link = GetFirstNode (&HostBridge->RootBridges)\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
+ for (Index = TypeIo; Index < TypeBus; Index++) {\r
+ if (RootBridge->ResAllocNode[Index].Status == ResAllocated) {\r
+ switch (Index) {\r
+ case TypeIo:\r
+ Status = gDS->FreeIoSpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);\r
+ if (EFI_ERROR (Status)) {\r
+ ReturnStatus = Status;\r
+ }\r
+\r
+ break;\r
+\r
+ case TypeMem32:\r
+ case TypePMem32:\r
+ case TypeMem64:\r
+ case TypePMem64:\r
+ Status = gDS->FreeMemorySpace (RootBridge->ResAllocNode[Index].Base, RootBridge->ResAllocNode[Index].Length);\r
+ if (EFI_ERROR (Status)) {\r
+ ReturnStatus = Status;\r
+ }\r
+\r
+ break;\r
+\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
- break;\r
\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
+ RootBridge->ResAllocNode[Index].Type = Index;\r
+ RootBridge->ResAllocNode[Index].Base = 0;\r
+ RootBridge->ResAllocNode[Index].Length = 0;\r
+ RootBridge->ResAllocNode[Index].Status = ResNone;\r
}\r
-\r
- RootBridge->ResAllocNode[Index].Type = Index;\r
- RootBridge->ResAllocNode[Index].Base = 0;\r
- RootBridge->ResAllocNode[Index].Length = 0;\r
- RootBridge->ResAllocNode[Index].Status = ResNone;\r
}\r
- }\r
\r
- RootBridge->ResourceSubmitted = FALSE;\r
- }\r
+ RootBridge->ResourceSubmitted = FALSE;\r
+ }\r
\r
- HostBridge->CanRestarted = TRUE;\r
- return ReturnStatus;\r
+ HostBridge->CanRestarted = TRUE;\r
+ return ReturnStatus;\r
\r
- case EfiPciHostBridgeEndResourceAllocation:\r
- //\r
- // The resource allocation phase is completed. No specific action is required\r
- // here. This notification can be used to perform any chipset specific programming.\r
- //\r
- break;\r
+ case EfiPciHostBridgeEndResourceAllocation:\r
+ //\r
+ // The resource allocation phase is completed. No specific action is required\r
+ // here. This notification can be used to perform any chipset specific programming.\r
+ //\r
+ break;\r
\r
- case EfiPciHostBridgeEndEnumeration:\r
- //\r
- // The Host Bridge Enumeration is completed. No specific action is required here.\r
- // This notification can be used to perform any chipset specific programming.\r
- //\r
- break;\r
+ case EfiPciHostBridgeEndEnumeration:\r
+ //\r
+ // The Host Bridge Enumeration is completed. No specific action is required here.\r
+ // This notification can be used to perform any chipset specific programming.\r
+ //\r
+ break;\r
\r
- default:\r
- return EFI_INVALID_PARAMETER;\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
return EFI_SUCCESS;\r
EFI_STATUS\r
EFIAPI\r
GetNextRootBridge (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN OUT EFI_HANDLE *RootBridgeHandle\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN OUT EFI_HANDLE *RootBridgeHandle\r
)\r
{\r
BOOLEAN ReturnNext;\r
}\r
\r
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);\r
- ReturnNext = (BOOLEAN) (*RootBridgeHandle == NULL);\r
+ ReturnNext = (BOOLEAN)(*RootBridgeHandle == NULL);\r
\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
if (ReturnNext) {\r
*RootBridgeHandle = RootBridge->Handle;\r
return EFI_SUCCESS;\r
}\r
\r
- ReturnNext = (BOOLEAN) (*RootBridgeHandle == RootBridge->Handle);\r
+ ReturnNext = (BOOLEAN)(*RootBridgeHandle == RootBridge->Handle);\r
}\r
\r
if (ReturnNext) {\r
EFI_STATUS\r
EFIAPI\r
GetAttributes (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT UINT64 *Attributes\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT UINT64 *Attributes\r
)\r
{\r
LIST_ENTRY *Link;\r
\r
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
if (RootBridgeHandle == RootBridge->Handle) {\r
*Attributes = RootBridge->AllocationAttributes;\r
EFI_STATUS\r
EFIAPI\r
StartBusEnumeration (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
)\r
{\r
- LIST_ENTRY *Link;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
- EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
+ LIST_ENTRY *Link;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
\r
if (Configuration == NULL) {\r
return EFI_INVALID_PARAMETER;\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
; !IsNull (&HostBridge->RootBridges, Link)\r
; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
if (RootBridgeHandle == RootBridge->Handle) {\r
*Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) *Configuration;\r
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)*Configuration;\r
Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
Descriptor->AddrTranslationOffset = 0;\r
Descriptor->AddrLen = RootBridge->Bus.Limit - RootBridge->Bus.Base + 1;\r
\r
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);\r
- End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);\r
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
End->Checksum = 0x0;\r
\r
return EFI_SUCCESS;\r
EFI_STATUS\r
EFIAPI\r
SetBusNumbers (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
)\r
{\r
- LIST_ENTRY *Link;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
- EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
+ LIST_ENTRY *Link;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
\r
if (Configuration == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);\r
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;\r
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);\r
\r
//\r
// Check the Configuration is valid\r
if ((Descriptor->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) ||\r
(Descriptor->ResType != ACPI_ADDRESS_SPACE_TYPE_BUS) ||\r
(End->Desc != ACPI_END_TAG_DESCRIPTOR)\r
- ) {\r
+ )\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
; !IsNull (&HostBridge->RootBridges, Link)\r
; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
if (RootBridgeHandle == RootBridge->Handle) {\r
-\r
if (Descriptor->AddrLen == 0) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((Descriptor->AddrRangeMin < RootBridge->Bus.Base) ||\r
(Descriptor->AddrRangeMin + Descriptor->AddrLen - 1 > RootBridge->Bus.Limit)\r
- ) {\r
+ )\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
//\r
// Update the Bus Range\r
//\r
- RootBridge->ResAllocNode[TypeBus].Base = Descriptor->AddrRangeMin;\r
- RootBridge->ResAllocNode[TypeBus].Length = Descriptor->AddrLen;\r
- RootBridge->ResAllocNode[TypeBus].Status = ResAllocated;\r
+ RootBridge->ResAllocNode[TypeBus].Base = Descriptor->AddrRangeMin;\r
+ RootBridge->ResAllocNode[TypeBus].Length = Descriptor->AddrLen;\r
+ RootBridge->ResAllocNode[TypeBus].Status = ResAllocated;\r
return EFI_SUCCESS;\r
}\r
}\r
EFI_STATUS\r
EFIAPI\r
SubmitResources (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN VOID *Configuration\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
)\r
{\r
- LIST_ENTRY *Link;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
- PCI_RESOURCE_TYPE Type;\r
+ LIST_ENTRY *Link;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
+ PCI_RESOURCE_TYPE Type;\r
\r
//\r
// Check the input parameter: Configuration\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
; !IsNull (&HostBridge->RootBridges, Link)\r
; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
if (RootBridgeHandle == RootBridge->Handle) {\r
DEBUG ((DEBUG_INFO, "PciHostBridge: SubmitResources for %s\n", RootBridge->DevicePathStr));\r
// If the Configuration includes one or more invalid resource descriptors, all the resource\r
// descriptors are ignored and the function returns EFI_INVALID_PARAMETER.\r
//\r
- for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {\r
+ for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {\r
if (Descriptor->ResType > ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- DEBUG ((DEBUG_INFO, " %s: Granularity/SpecificFlag = %ld / %02x%s\n",\r
- mAcpiAddressSpaceTypeStr[Descriptor->ResType], Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,\r
- (Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0 ? L" (Prefetchable)" : L""\r
- ));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ " %s: Granularity/SpecificFlag = %ld / %02x%s\n",\r
+ mAcpiAddressSpaceTypeStr[Descriptor->ResType],\r
+ Descriptor->AddrSpaceGranularity,\r
+ Descriptor->SpecificFlag,\r
+ (Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0 ? L" (Prefetchable)" : L""\r
+ ));\r
DEBUG ((DEBUG_INFO, " Length/Alignment = 0x%lx / 0x%lx\n", Descriptor->AddrLen, Descriptor->AddrRangeMax));\r
switch (Descriptor->ResType) {\r
- case ACPI_ADDRESS_SPACE_TYPE_MEM:\r
- if (Descriptor->AddrSpaceGranularity != 32 && Descriptor->AddrSpaceGranularity != 64) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- if (Descriptor->AddrSpaceGranularity == 32 && Descriptor->AddrLen >= SIZE_4GB) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- //\r
- // If the PCI root bridge does not support separate windows for nonprefetchable and\r
- // prefetchable memory, then the PCI bus driver needs to include requests for\r
- // prefetchable memory in the nonprefetchable memory pool.\r
- //\r
- if (((RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) &&\r
- ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0)\r
- ) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- case ACPI_ADDRESS_SPACE_TYPE_IO:\r
- //\r
- // Check aligment, it should be of the form 2^n-1\r
- //\r
- if (GetPowerOfTwo64 (Descriptor->AddrRangeMax + 1) != (Descriptor->AddrRangeMax + 1)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
- break;\r
- default:\r
- ASSERT (FALSE);\r
- break;\r
+ case ACPI_ADDRESS_SPACE_TYPE_MEM:\r
+ if ((Descriptor->AddrSpaceGranularity != 32) && (Descriptor->AddrSpaceGranularity != 64)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((Descriptor->AddrSpaceGranularity == 32) && (Descriptor->AddrLen >= SIZE_4GB)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // If the PCI root bridge does not support separate windows for nonprefetchable and\r
+ // prefetchable memory, then the PCI bus driver needs to include requests for\r
+ // prefetchable memory in the nonprefetchable memory pool.\r
+ //\r
+ if (((RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) &&\r
+ ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0)\r
+ )\r
+ {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ case ACPI_ADDRESS_SPACE_TYPE_IO:\r
+ //\r
+ // Check aligment, it should be of the form 2^n-1\r
+ //\r
+ if (GetPowerOfTwo64 (Descriptor->AddrRangeMax + 1) != (Descriptor->AddrRangeMax + 1)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
+\r
if (Descriptor->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {\r
+ for (Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {\r
if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
if (Descriptor->AddrSpaceGranularity == 32) {\r
if ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0) {\r
ASSERT (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_IO);\r
Type = TypeIo;\r
}\r
+\r
RootBridge->ResAllocNode[Type].Length = Descriptor->AddrLen;\r
RootBridge->ResAllocNode[Type].Alignment = Descriptor->AddrRangeMax;\r
RootBridge->ResAllocNode[Type].Status = ResSubmitted;\r
}\r
+\r
RootBridge->ResourceSubmitted = TRUE;\r
return EFI_SUCCESS;\r
}\r
EFI_STATUS\r
EFIAPI\r
GetProposedResources (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- OUT VOID **Configuration\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
)\r
{\r
- LIST_ENTRY *Link;\r
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
- PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
- UINTN Index;\r
- UINTN Number;\r
- VOID *Buffer;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
- EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
- UINT64 ResStatus;\r
+ LIST_ENTRY *Link;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
+ UINTN Index;\r
+ UINTN Number;\r
+ VOID *Buffer;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
+ EFI_ACPI_END_TAG_DESCRIPTOR *End;\r
+ UINT64 ResStatus;\r
\r
HostBridge = PCI_HOST_BRIDGE_FROM_THIS (This);\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
- ; !IsNull (&HostBridge->RootBridges, Link)\r
- ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
if (RootBridgeHandle == RootBridge->Handle) {\r
for (Index = 0, Number = 0; Index < TypeBus; Index++) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Buffer;\r
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Buffer;\r
for (Index = 0; Index < TypeBus; Index++) {\r
ResStatus = RootBridge->ResAllocNode[Index].Status;\r
if (ResStatus != ResNone) {\r
- Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;;\r
- Descriptor->GenFlag = 0;\r
+ Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Descriptor->GenFlag = 0;\r
//\r
// AddrRangeMin in Resource Descriptor here should be device address\r
// instead of host address, or else PCI bus driver cannot set correct\r
// address into PCI BAR registers.\r
// Base in ResAllocNode is a host address, so conversion is needed.\r
//\r
- Descriptor->AddrRangeMin = TO_DEVICE_ADDRESS (RootBridge->ResAllocNode[Index].Base,\r
- GetTranslationByResourceType (RootBridge, Index));\r
+ Descriptor->AddrRangeMin = TO_DEVICE_ADDRESS (\r
+ RootBridge->ResAllocNode[Index].Base,\r
+ GetTranslationByResourceType (RootBridge, Index)\r
+ );\r
Descriptor->AddrRangeMax = 0;\r
Descriptor->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS;\r
Descriptor->AddrLen = RootBridge->ResAllocNode[Index].Length;\r
\r
switch (Index) {\r
+ case TypeIo:\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
+ break;\r
\r
- case TypeIo:\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
- break;\r
-\r
- case TypePMem32:\r
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
- case TypeMem32:\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Descriptor->AddrSpaceGranularity = 32;\r
- break;\r
+ case TypePMem32:\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
+ case TypeMem32:\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->AddrSpaceGranularity = 32;\r
+ break;\r
\r
- case TypePMem64:\r
- Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
- case TypeMem64:\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
- Descriptor->AddrSpaceGranularity = 64;\r
- break;\r
+ case TypePMem64:\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
+ case TypeMem64:\r
+ Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->AddrSpaceGranularity = 64;\r
+ break;\r
}\r
\r
Descriptor++;\r
}\r
}\r
- End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;\r
- End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
- End->Checksum = 0;\r
+\r
+ End = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;\r
+ End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ End->Checksum = 0;\r
\r
*Configuration = Buffer;\r
\r
EFI_STATUS\r
EFIAPI\r
PreprocessController (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
- IN EFI_HANDLE RootBridgeHandle,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
)\r
{\r
LIST_ENTRY *Link;\r
PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
\r
- if ((UINT32) Phase > EfiPciBeforeResourceCollection) {\r
+ if ((UINT32)Phase > EfiPciBeforeResourceCollection) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
for (Link = GetFirstNode (&HostBridge->RootBridges)\r
; !IsNull (&HostBridge->RootBridges, Link)\r
; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
- ) {\r
+ )\r
+ {\r
RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
if (RootBridgeHandle == RootBridge->Handle) {\r
return EFI_SUCCESS;\r
projects / mirror_edk2.git / blobdiff