#ifndef _SERIAL_H_\r
#define _SERIAL_H_\r
\r
-\r
#include <Uefi.h>\r
\r
#include <IndustryStandard/Pci.h>\r
//\r
// Driver Binding Externs\r
//\r
-extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r
-extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;\r
-extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;\r
+extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r
+extern EFI_COMPONENT_NAME_PROTOCOL gPciSioSerialComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gPciSioSerialComponentName2;\r
\r
-#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"\r
-#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"\r
-#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)\r
+#define SIO_SERIAL_PORT_NAME L"SIO Serial Port #%d"\r
+#define PCI_SERIAL_PORT_NAME L"PCI Serial Port #%d"\r
+#define SERIAL_PORT_NAME_LEN (sizeof (SIO_SERIAL_PORT_NAME) / sizeof (CHAR16) + MAXIMUM_VALUE_CHARACTERS)\r
\r
//\r
// Internal Data Structures\r
/// RegisterStride equals to 4.\r
///\r
typedef struct {\r
- UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
- UINT16 DeviceId; ///< Device ID to match the PCI device\r
- UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
- UINT64 Offset; ///< The byte offset into to the BAR\r
- UINT8 BarIndex; ///< Which BAR to get the UART base address\r
- UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
- UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
- UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
- UINT8 Reserved[2];\r
+ UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ UINT64 Offset; ///< The byte offset into to the BAR\r
+ UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ UINT8 Reserved[2];\r
} PCI_SERIAL_PARAMETER;\r
#pragma pack()\r
\r
-#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.\r
+#define SERIAL_MAX_FIFO_SIZE 17 ///< Actual FIFO size is 16. FIFO based on circular wastes one unit.\r
typedef struct {\r
- UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).\r
- UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).\r
- UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.\r
+ UINT16 Head; ///< Head pointer of the FIFO. Empty when (Head == Tail).\r
+ UINT16 Tail; ///< Tail pointer of the FIFO. Full when ((Tail + 1) % SERIAL_MAX_FIFO_SIZE == Head).\r
+ UINT8 Data[SERIAL_MAX_FIFO_SIZE]; ///< Store the FIFO data.\r
} SERIAL_DEV_FIFO;\r
\r
typedef union {\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- EFI_SIO_PROTOCOL *Sio;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_SIO_PROTOCOL *Sio;\r
} PARENT_IO_PROTOCOL_PTR;\r
\r
typedef struct {\r
- EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.\r
- UINTN ChildCount; // Count of child SerialIo instance.\r
- UINT64 PciAttributes; // Original PCI attributes.\r
+ EFI_PCI_IO_PROTOCOL *PciIo; // Pointer to parent PciIo instance.\r
+ UINTN ChildCount; // Count of child SerialIo instance.\r
+ UINT64 PciAttributes; // Original PCI attributes.\r
} PCI_DEVICE_INFO;\r
\r
typedef struct {\r
- UINT32 Signature;\r
- EFI_HANDLE Handle;\r
- EFI_SERIAL_IO_PROTOCOL SerialIo;\r
- EFI_SERIAL_IO_MODE SerialMode;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
-\r
- EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r
- UART_DEVICE_PATH UartDevicePath;\r
-\r
- EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address\r
- BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO\r
- UINT8 RegisterStride; ///< UART Register Stride\r
- UINT32 ClockRate; ///< UART clock rate\r
-\r
- UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.\r
- SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data\r
-\r
- UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.\r
- SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data\r
-\r
- BOOLEAN SoftwareLoopbackEnable;\r
- BOOLEAN HardwareFlowControl;\r
- EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
- BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node\r
- UINT32 Instance;\r
- PCI_DEVICE_INFO *PciDeviceInfo;\r
+ UINT32 Signature;\r
+ EFI_HANDLE Handle;\r
+ EFI_SERIAL_IO_PROTOCOL SerialIo;\r
+ EFI_SERIAL_IO_MODE SerialMode;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r
+ UART_DEVICE_PATH UartDevicePath;\r
+\r
+ EFI_PHYSICAL_ADDRESS BaseAddress; ///< UART base address\r
+ BOOLEAN MmioAccess; ///< TRUE for MMIO, FALSE for IO\r
+ UINT8 RegisterStride; ///< UART Register Stride\r
+ UINT32 ClockRate; ///< UART clock rate\r
+\r
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes.\r
+ SERIAL_DEV_FIFO Receive; ///< The FIFO used to store received data\r
+\r
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes.\r
+ SERIAL_DEV_FIFO Transmit; ///< The FIFO used to store to-transmit data\r
+\r
+ BOOLEAN SoftwareLoopbackEnable;\r
+ BOOLEAN HardwareFlowControl;\r
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r
+ BOOLEAN ContainsControllerNode; ///< TRUE if the device produced contains Controller node\r
+ UINT32 Instance;\r
+ PCI_DEVICE_INFO *PciDeviceInfo;\r
} SERIAL_DEV;\r
\r
-#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')\r
-#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)\r
+#define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')\r
+#define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)\r
\r
//\r
// Serial Driver Defaults\r
//\r
-#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000\r
-#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \\r
+#define SERIAL_PORT_DEFAULT_TIMEOUT 1000000\r
+#define SERIAL_PORT_SUPPORT_CONTROL_MASK (EFI_SERIAL_CLEAR_TO_SEND | \\r
EFI_SERIAL_DATA_SET_READY | \\r
EFI_SERIAL_RING_INDICATE | \\r
EFI_SERIAL_CARRIER_DETECT | \\r
EFI_SERIAL_OUTPUT_BUFFER_EMPTY | \\r
EFI_SERIAL_INPUT_BUFFER_EMPTY)\r
\r
-#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS\r
-#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds\r
+#define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS\r
+#define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds\r
//\r
// UART Registers\r
//\r
-#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register\r
-#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register\r
-#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB\r
-#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB\r
-#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register\r
-#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register\r
-#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register\r
-#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register\r
-#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register\r
-#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register\r
-#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register\r
-#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register\r
+#define SERIAL_REGISTER_THR 0 ///< WO Transmit Holding Register\r
+#define SERIAL_REGISTER_RBR 0 ///< RO Receive Buffer Register\r
+#define SERIAL_REGISTER_DLL 0 ///< R/W Divisor Latch LSB\r
+#define SERIAL_REGISTER_DLM 1 ///< R/W Divisor Latch MSB\r
+#define SERIAL_REGISTER_IER 1 ///< R/W Interrupt Enable Register\r
+#define SERIAL_REGISTER_IIR 2 ///< RO Interrupt Identification Register\r
+#define SERIAL_REGISTER_FCR 2 ///< WO FIFO Cotrol Register\r
+#define SERIAL_REGISTER_LCR 3 ///< R/W Line Control Register\r
+#define SERIAL_REGISTER_MCR 4 ///< R/W Modem Control Register\r
+#define SERIAL_REGISTER_LSR 5 ///< R/W Line Status Register\r
+#define SERIAL_REGISTER_MSR 6 ///< R/W Modem Status Register\r
+#define SERIAL_REGISTER_SCR 7 ///< R/W Scratch Pad Register\r
#pragma pack(1)\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable\r
- UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable\r
- UINT8 Rie : 1; ///< Receiver Interrupt Enable\r
- UINT8 Mie : 1; ///< Modem Interrupt Enable\r
- UINT8 Reserved : 4;\r
+ UINT8 Ravie : 1; ///< Receiver Data Available Interrupt Enable\r
+ UINT8 Theie : 1; ///< Transmistter Holding Register Empty Interrupt Enable\r
+ UINT8 Rie : 1; ///< Receiver Interrupt Enable\r
+ UINT8 Mie : 1; ///< Modem Interrupt Enable\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SERIAL_PORT_IER;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable\r
- UINT8 ResetRF : 1; ///< Reset Reciever FIFO\r
- UINT8 ResetTF : 1; ///< Reset Transmistter FIFO\r
- UINT8 Dms : 1; ///< DMA Mode Select\r
- UINT8 Reserved : 1;\r
- UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO\r
- UINT8 Rtb : 2; ///< Receive Trigger Bits\r
+ UINT8 TrFIFOE : 1; ///< Transmit and Receive FIFO Enable\r
+ UINT8 ResetRF : 1; ///< Reset Reciever FIFO\r
+ UINT8 ResetTF : 1; ///< Reset Transmistter FIFO\r
+ UINT8 Dms : 1; ///< DMA Mode Select\r
+ UINT8 Reserved : 1;\r
+ UINT8 TrFIFO64 : 1; ///< Enable 64 byte FIFO\r
+ UINT8 Rtb : 2; ///< Receive Trigger Bits\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SERIAL_PORT_FCR;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT8 SerialDB : 2; ///< Number of Serial Data Bits\r
- UINT8 StopB : 1; ///< Number of Stop Bits\r
- UINT8 ParEn : 1; ///< Parity Enable\r
- UINT8 EvenPar : 1; ///< Even Parity Select\r
- UINT8 SticPar : 1; ///< Sticky Parity\r
- UINT8 BrCon : 1; ///< Break Control\r
- UINT8 DLab : 1; ///< Divisor Latch Access Bit\r
+ UINT8 SerialDB : 2; ///< Number of Serial Data Bits\r
+ UINT8 StopB : 1; ///< Number of Stop Bits\r
+ UINT8 ParEn : 1; ///< Parity Enable\r
+ UINT8 EvenPar : 1; ///< Even Parity Select\r
+ UINT8 SticPar : 1; ///< Sticky Parity\r
+ UINT8 BrCon : 1; ///< Break Control\r
+ UINT8 DLab : 1; ///< Divisor Latch Access Bit\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SERIAL_PORT_LCR;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT8 DtrC : 1; ///< Data Terminal Ready Control\r
- UINT8 Rts : 1; ///< Request To Send Control\r
- UINT8 Out1 : 1; ///< Output1\r
- UINT8 Out2 : 1; ///< Output2, used to disable interrupt\r
- UINT8 Lme : 1; ///< Loopback Mode Enable\r
- UINT8 Reserved : 3;\r
+ UINT8 DtrC : 1; ///< Data Terminal Ready Control\r
+ UINT8 Rts : 1; ///< Request To Send Control\r
+ UINT8 Out1 : 1; ///< Output1\r
+ UINT8 Out2 : 1; ///< Output2, used to disable interrupt\r
+ UINT8 Lme : 1; ///< Loopback Mode Enable\r
+ UINT8 Reserved : 3;\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SERIAL_PORT_MCR;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT8 Dr : 1; ///< Receiver Data Ready Status\r
- UINT8 Oe : 1; ///< Overrun Error Status\r
- UINT8 Pe : 1; ///< Parity Error Status\r
- UINT8 Fe : 1; ///< Framing Error Status\r
- UINT8 Bi : 1; ///< Break Interrupt Status\r
- UINT8 Thre : 1; ///< Transmistter Holding Register Status\r
- UINT8 Temt : 1; ///< Transmitter Empty Status\r
- UINT8 FIFOe : 1; ///< FIFO Error Status\r
+ UINT8 Dr : 1; ///< Receiver Data Ready Status\r
+ UINT8 Oe : 1; ///< Overrun Error Status\r
+ UINT8 Pe : 1; ///< Parity Error Status\r
+ UINT8 Fe : 1; ///< Framing Error Status\r
+ UINT8 Bi : 1; ///< Break Interrupt Status\r
+ UINT8 Thre : 1; ///< Transmistter Holding Register Status\r
+ UINT8 Temt : 1; ///< Transmitter Empty Status\r
+ UINT8 FIFOe : 1; ///< FIFO Error Status\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SERIAL_PORT_LSR;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status\r
- UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status\r
- UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status\r
- UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status\r
- UINT8 Cts : 1; ///< Clear To Send Status\r
- UINT8 Dsr : 1; ///< Data Set Ready Status\r
- UINT8 Ri : 1; ///< Ring Indicator Status\r
- UINT8 Dcd : 1; ///< Data Carrier Detect Status\r
+ UINT8 DeltaCTS : 1; ///< Delta Clear To Send Status\r
+ UINT8 DeltaDSR : 1; ///< Delta Data Set Ready Status\r
+ UINT8 TrailingEdgeRI : 1; ///< Trailing Edge of Ring Indicator Status\r
+ UINT8 DeltaDCD : 1; ///< Delta Data Carrier Detect Status\r
+ UINT8 Cts : 1; ///< Clear To Send Status\r
+ UINT8 Dsr : 1; ///< Data Set Ready Status\r
+ UINT8 Ri : 1; ///< Ring Indicator Status\r
+ UINT8 Dcd : 1; ///< Data Carrier Detect Status\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SERIAL_PORT_MSR;\r
\r
#pragma pack()\r
//\r
// Define serial register I/O macros\r
//\r
-#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)\r
-#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)\r
-#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)\r
-#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)\r
-#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)\r
-#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)\r
-#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)\r
-#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)\r
-#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)\r
-#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)\r
-\r
-#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)\r
-#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)\r
-#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)\r
-#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)\r
-#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)\r
-#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)\r
-#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)\r
-#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)\r
-#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)\r
-#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)\r
+#define READ_RBR(S) SerialReadRegister (S, SERIAL_REGISTER_RBR)\r
+#define READ_DLL(S) SerialReadRegister (S, SERIAL_REGISTER_DLL)\r
+#define READ_DLM(S) SerialReadRegister (S, SERIAL_REGISTER_DLM)\r
+#define READ_IER(S) SerialReadRegister (S, SERIAL_REGISTER_IER)\r
+#define READ_IIR(S) SerialReadRegister (S, SERIAL_REGISTER_IIR)\r
+#define READ_LCR(S) SerialReadRegister (S, SERIAL_REGISTER_LCR)\r
+#define READ_MCR(S) SerialReadRegister (S, SERIAL_REGISTER_MCR)\r
+#define READ_LSR(S) SerialReadRegister (S, SERIAL_REGISTER_LSR)\r
+#define READ_MSR(S) SerialReadRegister (S, SERIAL_REGISTER_MSR)\r
+#define READ_SCR(S) SerialReadRegister (S, SERIAL_REGISTER_SCR)\r
+\r
+#define WRITE_THR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_THR, D)\r
+#define WRITE_DLL(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLL, D)\r
+#define WRITE_DLM(S, D) SerialWriteRegister (S, SERIAL_REGISTER_DLM, D)\r
+#define WRITE_IER(S, D) SerialWriteRegister (S, SERIAL_REGISTER_IER, D)\r
+#define WRITE_FCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_FCR, D)\r
+#define WRITE_LCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LCR, D)\r
+#define WRITE_MCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MCR, D)\r
+#define WRITE_LSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_LSR, D)\r
+#define WRITE_MSR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_MSR, D)\r
+#define WRITE_SCR(S, D) SerialWriteRegister (S, SERIAL_REGISTER_SCR, D)\r
\r
//\r
// Prototypes\r
// Driver model protocol interface\r
//\r
+\r
/**\r
Check to see if this driver supports the given controller\r
\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverSupported (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverStart (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SerialControllerDriverStop (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN UINTN NumberOfChildren,\r
- IN EFI_HANDLE *ChildHandleBuffer\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
);\r
\r
//\r
// Serial I/O Protocol Interface\r
//\r
+\r
/**\r
Reset serial device.\r
\r
EFI_STATUS\r
EFIAPI\r
SerialReset (\r
- IN EFI_SERIAL_IO_PROTOCOL *This\r
+ IN EFI_SERIAL_IO_PROTOCOL *This\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SerialSetAttributes (\r
- IN EFI_SERIAL_IO_PROTOCOL *This,\r
- IN UINT64 BaudRate,\r
- IN UINT32 ReceiveFifoDepth,\r
- IN UINT32 Timeout,\r
- IN EFI_PARITY_TYPE Parity,\r
- IN UINT8 DataBits,\r
- IN EFI_STOP_BITS_TYPE StopBits\r
+ IN EFI_SERIAL_IO_PROTOCOL *This,\r
+ IN UINT64 BaudRate,\r
+ IN UINT32 ReceiveFifoDepth,\r
+ IN UINT32 Timeout,\r
+ IN EFI_PARITY_TYPE Parity,\r
+ IN UINT8 DataBits,\r
+ IN EFI_STOP_BITS_TYPE StopBits\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SerialSetControl (\r
- IN EFI_SERIAL_IO_PROTOCOL *This,\r
- IN UINT32 Control\r
+ IN EFI_SERIAL_IO_PROTOCOL *This,\r
+ IN UINT32 Control\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SerialGetControl (\r
- IN EFI_SERIAL_IO_PROTOCOL *This,\r
- OUT UINT32 *Control\r
+ IN EFI_SERIAL_IO_PROTOCOL *This,\r
+ OUT UINT32 *Control\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SerialWrite (\r
- IN EFI_SERIAL_IO_PROTOCOL *This,\r
- IN OUT UINTN *BufferSize,\r
- IN VOID *Buffer\r
+ IN EFI_SERIAL_IO_PROTOCOL *This,\r
+ IN OUT UINTN *BufferSize,\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SerialRead (\r
- IN EFI_SERIAL_IO_PROTOCOL *This,\r
- IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer\r
+ IN EFI_SERIAL_IO_PROTOCOL *This,\r
+ IN OUT UINTN *BufferSize,\r
+ OUT VOID *Buffer\r
);\r
\r
//\r
// Internal Functions\r
//\r
+\r
/**\r
Use scratchpad register to test if this serial port is present.\r
\r
**/\r
BOOLEAN\r
SerialPresent (\r
- IN SERIAL_DEV *SerialDevice\r
+ IN SERIAL_DEV *SerialDevice\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
SerialFifoFull (\r
- IN SERIAL_DEV_FIFO *Fifo\r
+ IN SERIAL_DEV_FIFO *Fifo\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
SerialFifoEmpty (\r
- IN SERIAL_DEV_FIFO *Fifo\r
+ IN SERIAL_DEV_FIFO *Fifo\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
SerialFifoAdd (\r
- IN SERIAL_DEV_FIFO *Fifo,\r
- IN UINT8 Data\r
+ IN SERIAL_DEV_FIFO *Fifo,\r
+ IN UINT8 Data\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
SerialFifoRemove (\r
- IN SERIAL_DEV_FIFO *Fifo,\r
- OUT UINT8 *Data\r
+ IN SERIAL_DEV_FIFO *Fifo,\r
+ OUT UINT8 *Data\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
SerialReceiveTransmit (\r
- IN SERIAL_DEV *SerialDevice\r
+ IN SERIAL_DEV *SerialDevice\r
);\r
\r
/**\r
**/\r
UINT8\r
SerialReadRegister (\r
- IN SERIAL_DEV *SerialDev,\r
- IN UINT32 Offset\r
+ IN SERIAL_DEV *SerialDev,\r
+ IN UINT32 Offset\r
);\r
\r
/**\r
**/\r
VOID\r
SerialWriteRegister (\r
- IN SERIAL_DEV *SerialDev,\r
- IN UINT32 Offset,\r
- IN UINT8 Data\r
+ IN SERIAL_DEV *SerialDev,\r
+ IN UINT32 Offset,\r
+ IN UINT8 Data\r
);\r
\r
-\r
//\r
// EFI Component Name Functions\r
//\r
+\r
/**\r
Retrieves a Unicode string that is the user readable name of the driver.\r
\r
OUT CHAR16 **DriverName\r
);\r
\r
-\r
/**\r
Retrieves a Unicode string that is the user readable name of the controller\r
that is being managed by a driver.\r
EFI_STATUS\r
EFIAPI\r
SerialComponentNameGetControllerName (\r
- IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
- IN EFI_HANDLE ControllerHandle,\r
- IN EFI_HANDLE ChildHandle OPTIONAL,\r
- IN CHAR8 *Language,\r
- OUT CHAR16 **ControllerName\r
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
+ IN EFI_HANDLE ControllerHandle,\r
+ IN EFI_HANDLE ChildHandle OPTIONAL,\r
+ IN CHAR8 *Language,\r
+ OUT CHAR16 **ControllerName\r
);\r
\r
/**\r
**/\r
VOID\r
AddName (\r
- IN SERIAL_DEV *SerialDevice,\r
- IN UINT32 Uid\r
+ IN SERIAL_DEV *SerialDevice,\r
+ IN UINT32 Uid\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
VerifyUartParameters (\r
- IN UINT32 ClockRate,\r
- IN UINT64 BaudRate,\r
- IN UINT8 DataBits,\r
- IN EFI_PARITY_TYPE Parity,\r
- IN EFI_STOP_BITS_TYPE StopBits,\r
- OUT UINT64 *Divisor,\r
- OUT UINT64 *ActualBaudRate\r
+ IN UINT32 ClockRate,\r
+ IN UINT64 BaudRate,\r
+ IN UINT8 DataBits,\r
+ IN EFI_PARITY_TYPE Parity,\r
+ IN EFI_STOP_BITS_TYPE StopBits,\r
+ OUT UINT64 *Divisor,\r
+ OUT UINT64 *ActualBaudRate\r
);\r
\r
/**\r
**/\r
UART_DEVICE_PATH *\r
SkipControllerDevicePathNode (\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- BOOLEAN *ContainsControllerNode,\r
- UINT32 *ControllerNumber\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ BOOLEAN *ContainsControllerNode,\r
+ UINT32 *ControllerNumber\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsUartFlowControlDevicePathNode (\r
- IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl\r
+ IN UART_FLOW_CONTROL_DEVICE_PATH *FlowControl\r
);\r
+\r
#endif\r
projects / mirror_edk2.git / blobdiff