MdeModulePkg/PciSioSerialDxe: Do not flush the UART

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciSioSerialDxe / SerialIo.c

diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
index f1870f3a1bed1e17592f9f3accc405b21a4648e2..cce61d7a239817cf216b9fed8df95096c5197db7 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
+++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
@@ -1,7 +1,7 @@
 /** @file\r
   SerialIo implementation for PCI or SIO UARTs.\r
 \r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -442,27 +442,6 @@ SerialReceiveTransmit (
   return EFI_SUCCESS;\r
 }\r
 \r
-/**\r
-  Flush the serial hardware transmit FIFO and shift register.\r
-\r
-  @param SerialDevice  The device to flush.\r
-**/\r
-VOID\r
-SerialFlushTransmitFifo (\r
-  SERIAL_DEV  *SerialDevice\r
-  )\r
-{\r
-  SERIAL_PORT_LSR  Lsr;\r
-\r
-  //\r
-  // Wait for the serial port to be ready, to make sure both the transmit FIFO\r
-  // and shift register empty.\r
-  //\r
-  do {\r
-    Lsr.Data = READ_LSR (SerialDevice);\r
-  } while (Lsr.Bits.Temt == 0);\r
-}\r
-\r
 //\r
 // Interface Functions\r
 //\r
@@ -503,8 +482,6 @@ SerialReset (
 \r
   Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
 \r
-  SerialFlushTransmitFifo (SerialDevice);\r
-\r
   //\r
   // Make sure DLAB is 0.\r
   //\r
@@ -683,8 +660,6 @@ SerialSetAttributes (
 \r
   Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
 \r
-  SerialFlushTransmitFifo (SerialDevice);\r
-\r
   //\r
   // Put serial port on Divisor Latch Mode\r
   //\r