/** @file\r
This file provides some helper functions which are specific for EMMC device.\r
\r
+ Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
SdMmcCmdBlk.ResponseType = 0;\r
SdMmcCmdBlk.CommandArgument = 0;\r
\r
+ gBS->Stall (1000);\r
+\r
Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);\r
\r
return Status;\r
do {\r
Status = EmmcSendTuningBlk (PassThru, Slot, BusWidth);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcTuningClkForHs200: Send tuning block fails with %r\n", Status));\r
+ DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails with %r\n", Status));\r
return Status;\r
}\r
\r
}\r
} while (++Retry < 40);\r
\r
- DEBUG ((EFI_D_ERROR, "EmmcTuningClkForHs200: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));\r
+ DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));\r
//\r
// Abort the tuning procedure and reset the tuning circuit.\r
//\r
return EFI_DEVICE_ERROR;\r
}\r
\r
+/**\r
+ Check the SWITCH operation status.\r
+\r
+ @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
+ @param[in] Slot The slot number on which command should be sent.\r
+ @param[in] Rca The relative device address.\r
+\r
+ @retval EFI_SUCCESS The SWITCH finished siccessfully.\r
+ @retval others The SWITCH failed.\r
+**/\r
+EFI_STATUS\r
+EmmcCheckSwitchStatus (\r
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r
+ IN UINT8 Slot,\r
+ IN UINT16 Rca\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT32 DevStatus;\r
+\r
+ Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails with %r\n", Status));\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Check the switch operation is really successful or not.\r
+ //\r
+ if ((DevStatus & BIT7) != 0) {\r
+ DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
/**\r
Switch the bus width to specified width.\r
\r
UINT8 Index;\r
UINT8 Value;\r
UINT8 CmdSet;\r
- UINT32 DevStatus;\r
\r
//\r
// Write Byte, the Value field is written into the byte pointed by Index.\r
CmdSet = 0;\r
Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSwitchBusWidth: Switch to bus width %d fails with %r\n", BusWidth, Status));\r
+ DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Switch to bus width %d fails with %r\n", BusWidth, Status));\r
return Status;\r
}\r
\r
- Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);\r
+ Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n", Status));\r
return Status;\r
}\r
- //\r
- // Check the switch operation is really successful or not.\r
- //\r
- if ((DevStatus & BIT7) != 0) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSwitchBusWidth: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));\r
- return EFI_DEVICE_ERROR;\r
- }\r
\r
Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);\r
\r
}\r
\r
/**\r
- Switch the clock frequency to the specified value.\r
+ Switch the bus timing and clock frequency.\r
\r
Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller\r
Simplified Spec 3.0 Figure 3-3 for details.\r
\r
- @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
- @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
- @param[in] Slot The slot number of the SD card to send the command to.\r
- @param[in] Rca The relative device address to be assigned.\r
- @param[in] HsTiming The value to be written to HS_TIMING field of EXT_CSD register.\r
- @param[in] ClockFreq The max clock frequency to be set, the unit is MHz.\r
+ @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[in] Rca The relative device address to be assigned.\r
+ @param[in] DriverStrength Driver strength to set for speed modes that support it.\r
+ @param[in] BusTiming The bus mode timing indicator.\r
+ @param[in] ClockFreq The max clock frequency to be set, the unit is MHz.\r
\r
@retval EFI_SUCCESS The operation is done correctly.\r
@retval Others The operation fails.\r
\r
**/\r
EFI_STATUS\r
-EmmcSwitchClockFreq (\r
+EmmcSwitchBusTiming (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r
IN UINT8 Slot,\r
IN UINT16 Rca,\r
- IN UINT8 HsTiming,\r
+ IN EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength,\r
+ IN SD_MMC_BUS_MODE BusTiming,\r
IN UINT32 ClockFreq\r
)\r
{\r
UINT8 Index;\r
UINT8 Value;\r
UINT8 CmdSet;\r
- UINT32 DevStatus;\r
SD_MMC_HC_PRIVATE_DATA *Private;\r
+ UINT8 HostCtrl1;\r
+ BOOLEAN DelaySendStatus;\r
\r
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);\r
//\r
//\r
Access = 0x03;\r
Index = OFFSET_OF (EMMC_EXT_CSD, HsTiming);\r
- Value = HsTiming;\r
CmdSet = 0;\r
+ switch (BusTiming) {\r
+ case SdMmcMmcHs400:\r
+ Value = (UINT8)((DriverStrength.Emmc << 4) | 3);\r
+ break;\r
+ case SdMmcMmcHs200:\r
+ Value = (UINT8)((DriverStrength.Emmc << 4) | 2);\r
+ break;\r
+ case SdMmcMmcHsSdr:\r
+ case SdMmcMmcHsDdr:\r
+ Value = 1;\r
+ break;\r
+ case SdMmcMmcLegacy:\r
+ Value = 0;\r
+ break;\r
+ default:\r
+ DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d)\n", BusTiming));\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
\r
Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSwitchClockFreq: Switch to hstiming %d fails with %r\n", HsTiming, Status));\r
+ DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Switch to bus timing %d fails with %r\n", BusTiming, Status));\r
return Status;\r
}\r
\r
- Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);\r
+ if (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcHsDdr) {\r
+ HostCtrl1 = BIT2;\r
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ } else {\r
+ HostCtrl1 = (UINT8)~BIT2;\r
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+\r
+ Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, BusTiming);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSwitchClockFreq: Send status fails with %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
- // Check the switch operation is really successful or not.\r
+ // For cases when we switch bus timing to higher mode from current we want to\r
+ // send SEND_STATUS at current, lower, frequency then the target frequency to avoid\r
+ // stability issues. It has been observed that some designs are unable to process the\r
+ // SEND_STATUS at higher frequency during switch to HS200 @200MHz irrespective of the number of retries\r
+ // and only running the clock tuning is able to make them work at target frequency.\r
//\r
- if ((DevStatus & BIT7) != 0) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSwitchClockFreq: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));\r
- return EFI_DEVICE_ERROR;\r
+ // For cases when we are downgrading the frequency and current high frequency is invalid\r
+ // we have to first change the frequency to target frequency and then send the SEND_STATUS.\r
+ //\r
+ if (Private->Slot[Slot].CurrentFreq < (ClockFreq * 1000)) {\r
+ Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ DelaySendStatus = FALSE;\r
+ } else {\r
+ DelaySendStatus = TRUE;\r
}\r
+\r
//\r
// Convert the clock freq unit from MHz to KHz.\r
//\r
- Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->Capability[Slot]);\r
+ Status = SdMmcHcClockSupply (Private, Slot, BusTiming, FALSE, ClockFreq * 1000);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if (DelaySendStatus) {\r
+ Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
\r
return Status;\r
}\r
@param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
@param[in] Slot The slot number of the SD card to send the command to.\r
@param[in] Rca The relative device address to be assigned.\r
- @param[in] ClockFreq The max clock frequency to be set.\r
- @param[in] IsDdr If TRUE, use dual data rate data simpling method. Otherwise\r
- use single data rate data simpling method.\r
- @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r
+ @param[in] BusMode Pointer to SD_MMC_BUS_SETTINGS structure containing bus settings.\r
\r
@retval EFI_SUCCESS The operation is done correctly.\r
@retval Others The operation fails.\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r
IN UINT8 Slot,\r
IN UINT16 Rca,\r
- IN UINT32 ClockFreq,\r
- IN BOOLEAN IsDdr,\r
- IN UINT8 BusWidth\r
+ IN SD_MMC_BUS_SETTINGS *BusMode\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HsTiming;\r
- UINT8 HostCtrl1;\r
- UINT8 HostCtrl2;\r
+ EFI_STATUS Status;\r
+ BOOLEAN IsDdr;\r
\r
- Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Set to Hight Speed timing\r
- //\r
- HostCtrl1 = BIT2;\r
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
+ if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != SdMmcMmcHsDdr && BusMode->BusTiming != SdMmcMmcLegacy) ||\r
+ BusMode->ClockFreq > 52) {\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
- //\r
- // Clean UHS Mode Select field of Host Control 2 reigster before update\r
- //\r
- HostCtrl2 = (UINT8)~0x7;\r
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50\r
- //\r
- if (IsDdr) {\r
- HostCtrl2 = BIT2;\r
- } else if (ClockFreq == 52) {\r
- HostCtrl2 = BIT0;\r
+ if (BusMode->BusTiming == SdMmcMmcHsDdr) {\r
+ IsDdr = TRUE;\r
} else {\r
- HostCtrl2 = 0;\r
- }\r
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
+ IsDdr = FALSE;\r
}\r
\r
- HsTiming = 1;\r
- Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);\r
+ Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusMode->BusWidth);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- return Status;\r
+ return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);\r
}\r
\r
/**\r
- Switch to the HS200 timing according to request.\r
+ Switch to the HS200 timing. This function assumes that eMMC bus is still in legacy mode.\r
\r
Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
Simplified Spec 3.0 Figure 2-29 for details.\r
\r
- @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
- @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
- @param[in] Slot The slot number of the SD card to send the command to.\r
- @param[in] Rca The relative device address to be assigned.\r
- @param[in] ClockFreq The max clock frequency to be set.\r
- @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r
+ @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[in] Rca The relative device address to be assigned.\r
+ @param[in] BusMode Pointer to SD_MMC_BUS_SETTINGS structure containing bus settings.\r
\r
@retval EFI_SUCCESS The operation is done correctly.\r
@retval Others The operation fails.\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r
IN UINT8 Slot,\r
IN UINT16 Rca,\r
- IN UINT32 ClockFreq,\r
- IN UINT8 BusWidth\r
+ IN SD_MMC_BUS_SETTINGS *BusMode\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HsTiming;\r
- UINT8 HostCtrl2;\r
- UINT16 ClockCtrl;\r
+ EFI_STATUS Status;\r
\r
- if ((BusWidth != 4) && (BusWidth != 8)) {\r
+ if (BusMode->BusTiming != SdMmcMmcHs200 ||\r
+ (BusMode->BusWidth != 4 && BusMode->BusWidth != 8)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, FALSE, BusWidth);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Set to HS200/SDR104 timing\r
- //\r
- //\r
- // Stop bus clock at first\r
- //\r
- Status = SdMmcHcStopClock (PciIo, Slot);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Clean UHS Mode Select field of Host Control 2 reigster before update\r
- //\r
- HostCtrl2 = (UINT8)~0x7;\r
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, FALSE, BusMode->BusWidth);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- //\r
- // Set UHS Mode Select field of Host Control 2 reigster to SDR104\r
- //\r
- HostCtrl2 = BIT0 | BIT1;\r
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit\r
- //\r
- Status = SdMmcHcWaitMmioSet (\r
- PciIo,\r
- Slot,\r
- SD_MMC_HC_CLOCK_CTRL,\r
- sizeof (ClockCtrl),\r
- BIT1,\r
- BIT1,\r
- SD_MMC_HC_GENERIC_TIMEOUT\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- //\r
- // Set SD Clock Enable in the Clock Control register to 1\r
- //\r
- ClockCtrl = BIT2;\r
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
- HsTiming = 2;\r
- Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);\r
+ Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);\r
+ Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusMode->BusWidth);\r
\r
return Status;\r
}\r
\r
/**\r
- Switch to the HS400 timing according to request.\r
+ Switch to the HS400 timing. This function assumes that eMMC bus is still in legacy mode.\r
\r
Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
Simplified Spec 3.0 Figure 2-29 for details.\r
\r
- @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
- @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
- @param[in] Slot The slot number of the SD card to send the command to.\r
- @param[in] Rca The relative device address to be assigned.\r
- @param[in] ClockFreq The max clock frequency to be set.\r
+ @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[in] Rca The relative device address to be assigned.\r
+ @param[in] BusMode Pointer to SD_MMC_BUS_SETTINGS structure containing bus settings.\r
\r
@retval EFI_SUCCESS The operation is done correctly.\r
@retval Others The operation fails.\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,\r
IN UINT8 Slot,\r
IN UINT16 Rca,\r
- IN UINT32 ClockFreq\r
+ IN SD_MMC_BUS_SETTINGS *BusMode\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HsTiming;\r
- UINT8 HostCtrl2;\r
+ EFI_STATUS Status;\r
+ SD_MMC_BUS_SETTINGS Hs200BusMode;\r
+ UINT32 HsFreq;\r
\r
- Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
+ if (BusMode->BusTiming != SdMmcMmcHs400 ||\r
+ BusMode->BusWidth != 8) {\r
+ return EFI_INVALID_PARAMETER;\r
}\r
- //\r
- // Set to Hight Speed timing and set the clock frequency to a value less than 52MHz.\r
- //\r
- HsTiming = 1;\r
- Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, 52);\r
+\r
+ Hs200BusMode.BusTiming = SdMmcMmcHs200;\r
+ Hs200BusMode.BusWidth = BusMode->BusWidth;\r
+ Hs200BusMode.ClockFreq = BusMode->ClockFreq;\r
+ Hs200BusMode.DriverStrength = BusMode->DriverStrength;\r
+\r
+ Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, &Hs200BusMode);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
- // HS400 mode must use 8 data lines.\r
+ // Set to High Speed timing and set the clock frequency to a value less than or equal to 52MHz.\r
+ // This step is necessary to be able to switch Bus into 8 bit DDR mode which is unsupported in HS200.\r
//\r
- Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, TRUE, 8);\r
+ HsFreq = BusMode->ClockFreq < 52 ? BusMode->ClockFreq : 52;\r
+ Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, SdMmcMmcHsSdr, HsFreq);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- //\r
- // Clean UHS Mode Select field of Host Control 2 reigster before update\r
- //\r
- HostCtrl2 = (UINT8)~0x7;\r
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+\r
+ Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, TRUE, BusMode->BusWidth);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
+ return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);\r
+}\r
+\r
+/**\r
+ Check if passed BusTiming is supported in both controller and card.\r
+\r
+ @param[in] Private Pointer to controller private data\r
+ @param[in] SlotIndex Index of the slot in the controller\r
+ @param[in] ExtCsd Pointer to the card's extended CSD\r
+ @param[in] BusTiming Bus timing to check\r
+\r
+ @retval TRUE Both card and controller support given BusTiming\r
+ @retval FALSE Card or controller doesn't support given BusTiming\r
+**/\r
+BOOLEAN\r
+EmmcIsBusTimingSupported (\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 SlotIndex,\r
+ IN EMMC_EXT_CSD *ExtCsd,\r
+ IN SD_MMC_BUS_MODE BusTiming\r
+ )\r
+{\r
+ BOOLEAN Supported;\r
+ SD_MMC_HC_SLOT_CAP *Capabilities;\r
+\r
+ Capabilities = &Private->Capability[SlotIndex];\r
+\r
+ Supported = FALSE;\r
+ switch (BusTiming) {\r
+ case SdMmcMmcHs400:\r
+ if ((((ExtCsd->DeviceType & (BIT6 | BIT7)) != 0) && (Capabilities->Hs400 != 0)) && Capabilities->BusWidth8 != 0) {\r
+ Supported = TRUE;\r
+ }\r
+ break;\r
+ case SdMmcMmcHs200:\r
+ if ((((ExtCsd->DeviceType & (BIT4 | BIT5)) != 0) && (Capabilities->Sdr104 != 0))) {\r
+ Supported = TRUE;\r
+ }\r
+ break;\r
+ case SdMmcMmcHsDdr:\r
+ if ((((ExtCsd->DeviceType & (BIT2 | BIT3)) != 0) && (Capabilities->Ddr50 != 0))) {\r
+ Supported = TRUE;\r
+ }\r
+ break;\r
+ case SdMmcMmcHsSdr:\r
+ if ((((ExtCsd->DeviceType & BIT1) != 0) && (Capabilities->HighSpeed != 0))) {\r
+ Supported = TRUE;\r
+ }\r
+ break;\r
+ case SdMmcMmcLegacy:\r
+ if ((ExtCsd->DeviceType & BIT0) != 0) {\r
+ Supported = TRUE;\r
+ }\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ }\r
+\r
+ return Supported;\r
+}\r
+\r
+/**\r
+ Get the target bus timing to set on the link. This function\r
+ will try to select highest bus timing supported by card, controller\r
+ and the driver.\r
+\r
+ @param[in] Private Pointer to controller private data\r
+ @param[in] SlotIndex Index of the slot in the controller\r
+ @param[in] ExtCsd Pointer to the card's extended CSD\r
+\r
+ @return Bus timing value that should be set on link\r
+**/\r
+SD_MMC_BUS_MODE\r
+EmmcGetTargetBusTiming (\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 SlotIndex,\r
+ IN EMMC_EXT_CSD *ExtCsd\r
+ )\r
+{\r
+ SD_MMC_BUS_MODE BusTiming;\r
+\r
//\r
- // Set UHS Mode Select field of Host Control 2 reigster to HS400\r
+ // We start with highest bus timing that this driver currently supports and\r
+ // return as soon as we find supported timing.\r
//\r
- HostCtrl2 = BIT0 | BIT2;\r
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
+ BusTiming = SdMmcMmcHs400;\r
+ while (BusTiming > SdMmcMmcLegacy) {\r
+ if (EmmcIsBusTimingSupported (Private, SlotIndex, ExtCsd, BusTiming)) {\r
+ break;\r
+ }\r
+ BusTiming--;\r
}\r
\r
- HsTiming = 3;\r
- Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);\r
+ return BusTiming;\r
+}\r
\r
- return Status;\r
+/**\r
+ Check if the passed bus width is supported by controller and card.\r
+\r
+ @param[in] Private Pointer to controller private data\r
+ @param[in] SlotIndex Index of the slot in the controller\r
+ @param[in] BusTiming Bus timing set on the link\r
+ @param[in] BusWidth Bus width to check\r
+\r
+ @retval TRUE Passed bus width is supported in current bus configuration\r
+ @retval FALSE Passed bus width is not supported in current bus configuration\r
+**/\r
+BOOLEAN\r
+EmmcIsBusWidthSupported (\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 SlotIndex,\r
+ IN SD_MMC_BUS_MODE BusTiming,\r
+ IN UINT16 BusWidth\r
+ )\r
+{\r
+ if (BusWidth == 8 && Private->Capability[SlotIndex].BusWidth8 != 0) {\r
+ return TRUE;\r
+ } else if (BusWidth == 4 && BusTiming != SdMmcMmcHs400) {\r
+ return TRUE;\r
+ } else if (BusWidth == 1 && (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcLegacy)) {\r
+ return TRUE;\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Get the target bus width to be set on the bus.\r
+\r
+ @param[in] Private Pointer to controller private data\r
+ @param[in] SlotIndex Index of the slot in the controller\r
+ @param[in] ExtCsd Pointer to card's extended CSD\r
+ @param[in] BusTiming Bus timing set on the bus\r
+\r
+ @return Bus width to be set on the bus\r
+**/\r
+UINT8\r
+EmmcGetTargetBusWidth (\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 SlotIndex,\r
+ IN EMMC_EXT_CSD *ExtCsd,\r
+ IN SD_MMC_BUS_MODE BusTiming\r
+ )\r
+{\r
+ UINT8 BusWidth;\r
+ UINT8 PreferredBusWidth;\r
+\r
+ PreferredBusWidth = Private->Slot[SlotIndex].OperatingParameters.BusWidth;\r
+\r
+ if (PreferredBusWidth != EDKII_SD_MMC_BUS_WIDTH_IGNORE &&\r
+ EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, PreferredBusWidth)) {\r
+ BusWidth = PreferredBusWidth;\r
+ } else if (EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, 8)) {\r
+ BusWidth = 8;\r
+ } else if (EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, 4)) {\r
+ BusWidth = 4;\r
+ } else {\r
+ BusWidth = 1;\r
+ }\r
+\r
+ return BusWidth;\r
+}\r
+\r
+/**\r
+ Get the target clock frequency to be set on the bus.\r
+\r
+ @param[in] Private Pointer to controller private data\r
+ @param[in] SlotIndex Index of the slot in the controller\r
+ @param[in] ExtCsd Pointer to card's extended CSD\r
+ @param[in] BusTiming Bus timing to be set on the bus\r
+\r
+ @return Value of the clock frequency to be set on bus in MHz\r
+**/\r
+UINT32\r
+EmmcGetTargetClockFreq (\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 SlotIndex,\r
+ IN EMMC_EXT_CSD *ExtCsd,\r
+ IN SD_MMC_BUS_MODE BusTiming\r
+ )\r
+{\r
+ UINT32 PreferredClockFreq;\r
+ UINT32 MaxClockFreq;\r
+\r
+ PreferredClockFreq = Private->Slot[SlotIndex].OperatingParameters.ClockFreq;\r
+\r
+ switch (BusTiming) {\r
+ case SdMmcMmcHs400:\r
+ case SdMmcMmcHs200:\r
+ MaxClockFreq = 200;\r
+ break;\r
+ case SdMmcMmcHsSdr:\r
+ case SdMmcMmcHsDdr:\r
+ MaxClockFreq = 52;\r
+ break;\r
+ default:\r
+ MaxClockFreq = 26;\r
+ break;\r
+ }\r
+\r
+ if (PreferredClockFreq != EDKII_SD_MMC_CLOCK_FREQ_IGNORE && PreferredClockFreq < MaxClockFreq) {\r
+ return PreferredClockFreq;\r
+ } else {\r
+ return MaxClockFreq;\r
+ }\r
+}\r
+\r
+/**\r
+ Get the driver strength to be set on bus.\r
+\r
+ @param[in] Private Pointer to controller private data\r
+ @param[in] SlotIndex Index of the slot in the controller\r
+ @param[in] ExtCsd Pointer to card's extended CSD\r
+ @param[in] BusTiming Bus timing set on the bus\r
+\r
+ @return Value of the driver strength to be set on the bus\r
+**/\r
+EDKII_SD_MMC_DRIVER_STRENGTH\r
+EmmcGetTargetDriverStrength (\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 SlotIndex,\r
+ IN EMMC_EXT_CSD *ExtCsd,\r
+ IN SD_MMC_BUS_MODE BusTiming\r
+ )\r
+{\r
+ EDKII_SD_MMC_DRIVER_STRENGTH PreferredDriverStrength;\r
+ EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;\r
+\r
+ PreferredDriverStrength = Private->Slot[SlotIndex].OperatingParameters.DriverStrength;\r
+ DriverStrength.Emmc = EmmcDriverStrengthType0;\r
+\r
+ if (PreferredDriverStrength.Emmc != EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE &&\r
+ (ExtCsd->DriverStrength & (BIT0 << PreferredDriverStrength.Emmc))) {\r
+ DriverStrength.Emmc = PreferredDriverStrength.Emmc;\r
+ }\r
+\r
+ return DriverStrength;\r
+}\r
+\r
+/**\r
+ Get the target settings for the bus mode.\r
+\r
+ @param[in] Private Pointer to controller private data\r
+ @param[in] SlotIndex Index of the slot in the controller\r
+ @param[in] ExtCsd Pointer to card's extended CSD\r
+ @param[out] BusMode Target configuration of the bus\r
+**/\r
+VOID\r
+EmmcGetTargetBusMode (\r
+ IN SD_MMC_HC_PRIVATE_DATA *Private,\r
+ IN UINT8 SlotIndex,\r
+ IN EMMC_EXT_CSD *ExtCsd,\r
+ OUT SD_MMC_BUS_SETTINGS *BusMode\r
+ )\r
+{\r
+ BusMode->BusTiming = EmmcGetTargetBusTiming (Private, SlotIndex, ExtCsd);\r
+ BusMode->BusWidth = EmmcGetTargetBusWidth (Private, SlotIndex, ExtCsd, BusMode->BusTiming);\r
+ BusMode->ClockFreq = EmmcGetTargetClockFreq (Private, SlotIndex, ExtCsd, BusMode->BusTiming);\r
+ BusMode->DriverStrength = EmmcGetTargetDriverStrength (Private, SlotIndex, ExtCsd, BusMode->BusTiming);\r
}\r
\r
/**\r
EFI_STATUS Status;\r
EMMC_CSD Csd;\r
EMMC_EXT_CSD ExtCsd;\r
- UINT8 HsTiming;\r
- BOOLEAN IsDdr;\r
- UINT32 ClockFreq;\r
- UINT8 BusWidth;\r
+ SD_MMC_BUS_SETTINGS BusMode;\r
SD_MMC_HC_PRIVATE_DATA *Private;\r
\r
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);\r
\r
Status = EmmcGetCsd (PassThru, Slot, Rca, &Csd);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSetBusMode: GetCsd fails with %r\n", Status));\r
+ DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetCsd fails with %r\n", Status));\r
return Status;\r
}\r
\r
Status = EmmcSelect (PassThru, Slot, Rca);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSetBusMode: Select fails with %r\n", Status));\r
+ DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: Select fails with %r\n", Status));\r
return Status;\r
}\r
\r
- ASSERT (Private->Capability[Slot].BaseClkFreq != 0);\r
- //\r
- // Check if the Host Controller support 8bits bus width.\r
- //\r
- if (Private->Capability[Slot].BusWidth8 != 0) {\r
- BusWidth = 8;\r
- } else {\r
- BusWidth = 4;\r
- }\r
+ ASSERT (Private->BaseClkFreq[Slot] != 0);\r
+\r
//\r
- // Get Deivce_Type from EXT_CSD register.\r
+ // Get Device_Type from EXT_CSD register.\r
//\r
Status = EmmcGetExtCsd (PassThru, Slot, &ExtCsd);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcSetBusMode: GetExtCsd fails with %r\n", Status));\r
+ DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetExtCsd fails with %r\n", Status));\r
return Status;\r
}\r
- //\r
- // Calculate supported bus speed/bus width/clock frequency.\r
- //\r
- HsTiming = 0;\r
- IsDdr = FALSE;\r
- ClockFreq = 0;\r
- if (((ExtCsd.DeviceType & (BIT4 | BIT5)) != 0) && (Private->Capability[Slot].Sdr104 != 0)) {\r
- HsTiming = 2;\r
- IsDdr = FALSE;\r
- ClockFreq = 200;\r
- } else if (((ExtCsd.DeviceType & (BIT2 | BIT3)) != 0) && (Private->Capability[Slot].Ddr50 != 0)) {\r
- HsTiming = 1;\r
- IsDdr = TRUE;\r
- ClockFreq = 52;\r
- } else if (((ExtCsd.DeviceType & BIT1) != 0) && (Private->Capability[Slot].HighSpeed != 0)) {\r
- HsTiming = 1;\r
- IsDdr = FALSE;\r
- ClockFreq = 52;\r
- } else if (((ExtCsd.DeviceType & BIT0) != 0) && (Private->Capability[Slot].HighSpeed != 0)) {\r
- HsTiming = 1;\r
- IsDdr = FALSE;\r
- ClockFreq = 26;\r
- }\r
- //\r
- // Check if both of the device and the host controller support HS400 DDR mode.\r
- //\r
- if (((ExtCsd.DeviceType & (BIT6 | BIT7)) != 0) && (Private->Capability[Slot].Hs400 != 0)) {\r
- //\r
- // The host controller supports 8bits bus.\r
- //\r
- ASSERT (BusWidth == 8);\r
- HsTiming = 3;\r
- IsDdr = TRUE;\r
- ClockFreq = 200;\r
- }\r
\r
- if ((ClockFreq == 0) || (HsTiming == 0)) {\r
- //\r
- // Continue using default setting.\r
- //\r
- return EFI_SUCCESS;\r
- }\r
+ EmmcGetTargetBusMode (Private, Slot, &ExtCsd, &BusMode);\r
\r
- DEBUG ((EFI_D_INFO, "EmmcSetBusMode: HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));\r
+ DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Target bus mode: timing = %d, width = %d, clock freq = %d, driver strength = %d\n",\r
+ BusMode.BusTiming, BusMode.BusWidth, BusMode.ClockFreq, BusMode.DriverStrength.Emmc));\r
\r
- if (HsTiming == 3) {\r
- //\r
- // Execute HS400 timing switch procedure\r
- //\r
- Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, ClockFreq);\r
- } else if (HsTiming == 2) {\r
- //\r
- // Execute HS200 timing switch procedure\r
- //\r
- Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, BusWidth);\r
+ if (BusMode.BusTiming == SdMmcMmcHs400) {\r
+ Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, &BusMode);\r
+ } else if (BusMode.BusTiming == SdMmcMmcHs200) {\r
+ Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, &BusMode);\r
} else {\r
//\r
- // Execute High Speed timing switch procedure\r
+ // Note that EmmcSwitchToHighSpeed is also called for SdMmcMmcLegacy\r
+ // bus timing. This is because even though we might not want to\r
+ // change the timing itself we still want to allow customization of\r
+ // bus parameters such as clock frequency and bus width.\r
//\r
- Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, ClockFreq, IsDdr, BusWidth);\r
+ Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, &BusMode);\r
}\r
\r
- DEBUG ((EFI_D_INFO, "EmmcSetBusMode: Switch to %a %r\n", (HsTiming == 3) ? "HS400" : ((HsTiming == 2) ? "HS200" : "HighSpeed"), Status));\r
+ DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Switch to %a %r\n", (BusMode.BusTiming == SdMmcMmcHs400) ? "HS400" : ((BusMode.BusTiming == SdMmcMmcHs200) ? "HS200" : "HighSpeed"), Status));\r
\r
return Status;\r
}\r
EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru;\r
UINT32 Ocr;\r
UINT16 Rca;\r
+ UINTN Retry;\r
\r
PciIo = Private->PciIo;\r
PassThru = &Private->PassThru;\r
\r
Status = EmmcReset (PassThru, Slot);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_VERBOSE, "EmmcIdentification: Executing Cmd0 fails with %r\n", Status));\r
+ DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd0 fails with %r\n", Status));\r
return Status;\r
}\r
\r
- Ocr = 0;\r
+ Ocr = 0;\r
+ Retry = 0;\r
do {\r
Status = EmmcGetOcr (PassThru, Slot, &Ocr);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_VERBOSE, "EmmcIdentification: Executing Cmd1 fails with %r\n", Status));\r
+ DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails with %r\n", Status));\r
return Status;\r
}\r
Ocr |= BIT30;\r
+\r
+ if (Retry++ == 100) {\r
+ DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails too many times\n"));\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+ gBS->Stall(10 * 1000);\r
} while ((Ocr & BIT31) == 0);\r
\r
Status = EmmcGetAllCid (PassThru, Slot);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_VERBOSE, "EmmcIdentification: Executing Cmd2 fails with %r\n", Status));\r
+ DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd2 fails with %r\n", Status));\r
return Status;\r
}\r
//\r
Rca = Slot + 1;\r
Status = EmmcSetRca (PassThru, Slot, Rca);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "EmmcIdentification: Executing Cmd3 fails with %r\n", Status));\r
+ DEBUG ((DEBUG_ERROR, "EmmcIdentification: Executing Cmd3 fails with %r\n", Status));\r
return Status;\r
}\r
//\r
// Enter Data Tranfer Mode.\r
//\r
- DEBUG ((EFI_D_INFO, "EmmcIdentification: Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));\r
+ DEBUG ((DEBUG_INFO, "EmmcIdentification: Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));\r
Private->Slot[Slot].CardType = EmmcCardType;\r
\r
Status = EmmcSetBusMode (PciIo, PassThru, Slot, Rca);\r
projects / mirror_edk2.git / blobdiff