\r
Provides some data structure definitions used by the SD/MMC host controller driver.\r
\r
+Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.\r
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
SD_MMC_HC_SLOT Slot[SD_MMC_HC_MAX_SLOT];\r
SD_MMC_HC_SLOT_CAP Capability[SD_MMC_HC_MAX_SLOT];\r
UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];\r
+ UINT16 ControllerVersion[SD_MMC_HC_MAX_SLOT];\r
\r
- UINT32 ControllerVersion;\r
+ //\r
+ // Some controllers may require to override base clock frequency\r
+ // value stored in Capabilities Register 1.\r
+ //\r
+ UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];\r
} SD_MMC_HC_PRIVATE_DATA;\r
\r
#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')\r
EFI_PHYSICAL_ADDRESS DataPhy;\r
VOID *DataMap;\r
SD_MMC_HC_TRANSFER_MODE Mode;\r
+ SD_MMC_HC_ADMA_LENGTH_MODE AdmaLengthMode;\r
\r
EFI_EVENT Event;\r
BOOLEAN Started;\r
UINT64 Timeout;\r
\r
- SD_MMC_HC_ADMA_DESC_LINE *AdmaDesc;\r
+ SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;\r
+ SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc;\r
+ SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc;\r
EFI_PHYSICAL_ADDRESS AdmaDescPhy;\r
VOID *AdmaMap;\r
UINT32 AdmaPages;\r