UfsHcDxe driver is used to provide platform-dependent info, mainly UFS host controller\r
MMIO base, to upper layer UFS drivers.\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UfsHcFreeBuffer,\r
UfsHcMap,\r
UfsHcUnmap,\r
- UfsHcFlush\r
+ UfsHcFlush,\r
+ UfsHcMmioRead,\r
+ UfsHcMmioWrite\r
},\r
NULL, // PciIo\r
+ 0, // BarIndex\r
0 // PciAttributes\r
};\r
\r
UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
EFI_STATUS Status;\r
+ UINT8 BarIndex;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;\r
\r
if ((This == NULL) || (MmioBar == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);\r
- PciIo = Private->PciIo;\r
-\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- PCI_BASE_ADDRESSREG_OFFSET,\r
- sizeof (UINT32),\r
- MmioBar\r
- );\r
+ BarDesc = NULL;\r
+ Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);\r
+ PciIo = Private->PciIo;\r
+ BarIndex = Private->BarIndex;\r
\r
- if (!EFI_ERROR (Status)) {\r
- *MmioBar &= (UINTN)~0xF;\r
+ Status = PciIo->GetBarAttributes (\r
+ PciIo,\r
+ BarIndex,\r
+ NULL,\r
+ (VOID**) &BarDesc\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
}\r
+\r
+ *MmioBar = (UINTN)BarDesc->AddrRangeMin;\r
+\r
+ FreePool (BarDesc);\r
+\r
return Status;\r
}\r
\r
return Status;\r
}\r
\r
+/** \r
+ Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.\r
+\r
+ @param This A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Offset The offset within the UFS Host Controller MMIO space to start the\r
+ memory operation.\r
+ @param Count The number of memory operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results.\r
+ For write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the UFS host controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the UFS Host Controller memory space.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+UfsHcMmioRead (\r
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,\r
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_STATUS Status;\r
+ UINT8 BarIndex;\r
+\r
+ Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);\r
+ PciIo = Private->PciIo;\r
+ BarIndex = Private->BarIndex;\r
+\r
+ Status = PciIo->Mem.Read (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);\r
+\r
+ return Status;\r
+}\r
+\r
+/** \r
+ Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.\r
+\r
+ @param This A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Offset The offset within the UFS Host Controller MMIO space to start the\r
+ memory operation.\r
+ @param Count The number of memory operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results.\r
+ For write operations, the source buffer to write data from.\r
+\r
+ @retval EFI_SUCCESS The data was read from or written to the UFS host controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the UFS Host Controller memory space.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+UfsHcMmioWrite (\r
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,\r
+ IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Offset,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_STATUS Status;\r
+ UINT8 BarIndex;\r
+\r
+ Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);\r
+ PciIo = Private->PciIo;\r
+ BarIndex = Private->BarIndex;\r
+\r
+ Status = PciIo->Mem.Write (PciIo, (EFI_PCI_IO_PROTOCOL_WIDTH)Width, BarIndex, Offset, Count, Buffer);\r
+\r
+ return Status;\r
+}\r
+\r
/**\r
Tests to see if this driver supports a given controller. If a child device is provided,\r
it further tests to see if this driver supports creating a handle for the specified child device.\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UFS_HOST_CONTROLLER_PRIVATE_DATA *Private;\r
UINT64 Supports;\r
+ UINT8 BarIndex;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;\r
\r
PciIo = NULL;\r
Private = NULL;\r
Supports = 0;\r
+ BarDesc = NULL;\r
\r
//\r
// Now test and open the EfiPciIoProtocol\r
\r
Private->PciIo = PciIo;\r
\r
+ for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex++) {\r
+ Status = PciIo->GetBarAttributes (\r
+ PciIo,\r
+ BarIndex,\r
+ NULL,\r
+ (VOID**) &BarDesc\r
+ );\r
+ if (Status == EFI_UNSUPPORTED) {\r
+ continue;\r
+ } else if (EFI_ERROR (Status)) {\r
+ goto Done;\r
+ }\r
+\r
+ if (BarDesc->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
+ Private->BarIndex = BarIndex;\r
+ FreePool (BarDesc);\r
+ break;\r
+ }\r
+\r
+ FreePool (BarDesc);\r
+ }\r
+\r
Status = PciIo->Attributes (\r
PciIo,\r
EfiPciIoAttributeOperationGet,\r
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