/** @file\r
\r
-Copyright (c) 2007, Intel Corporation\r
+ The definition for UHCI register operation routines.\r
+\r
+Copyright (c) 2007 - 2008, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-Module Name:\r
-\r
- UhciReg.h\r
-\r
-Abstract:\r
-\r
- The definition for UHCI register operation routines.\r
-\r
-Revision History\r
-\r
-\r
**/\r
\r
#ifndef _EFI_UHCI_REG_H_\r
\r
#define BIT(a) (1 << (a))\r
\r
-enum {\r
+typedef enum {\r
UHCI_FRAME_NUM = 1024,\r
\r
//\r
USBPORTSC_PR = BIT(9), // Port Reset\r
USBPORTSC_SUSP = BIT(12), // Suspend\r
\r
- USB_MAX_ROOTHUB_PORT = 0x0F, // Max number of root hub port\r
-\r
+ //\r
+ // UHCI Spec said it must implement 2 ports each host at least,\r
+ // and if more, check whether the bit7 of PORTSC is always 1.\r
+ // So here assume the max of port number each host is 16.\r
+ //\r
+ USB_MAX_ROOTHUB_PORT = 0x0F,\r
+ \r
//\r
// Command register bit definitions\r
//\r
USBTD_NAK = BIT(3), // NAK is received\r
USBTD_CRC = BIT(2), // CRC/Time out error\r
USBTD_BITSTUFF = BIT(1) // Bit stuff error\r
-};\r
+}UHCI_REGISTER_OFFSET;\r
\r
\r
/**\r
- Read a UHCI register\r
+ Read a UHCI register.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Offset Register offset to USB_BAR_INDEX\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
\r
- @return Content of register\r
+ @return Content of register.\r
\r
**/\r
UINT16\r
UhciReadReg (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Write data to UHCI register\r
+ Write data to UHCI register.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Offset Register offset to USB_BAR_INDEX\r
- @param Data Data to write\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
+ @param Data Data to write.\r
\r
- @return VOID\r
+ @return None.\r
\r
**/\r
VOID\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset,\r
IN UINT16 Data\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Set a bit of the UHCI Register\r
+ Set a bit of the UHCI Register.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Offset Register offset to USB_BAR_INDEX\r
- @param Bit The bit to set\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
+ @param Bit The bit to set.\r
\r
- @return None\r
+ @return None.\r
\r
**/\r
VOID\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset,\r
IN UINT16 Bit\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Clear a bit of the UHCI Register\r
+ Clear a bit of the UHCI Register.\r
\r
- @param PciIo The PCI_IO protocol to access the PCI\r
- @param Offset Register offset to USB_BAR_INDEX\r
- @param Bit The bit to clear\r
+ @param PciIo The PCI_IO protocol to access the PCI.\r
+ @param Offset Register offset to USB_BAR_INDEX.\r
+ @param Bit The bit to clear.\r
\r
- @return None\r
+ @return None.\r
\r
**/\r
VOID\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN UINT32 Offset,\r
IN UINT16 Bit\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
Clear all the interrutp status bits, these bits\r
- are Write-Clean\r
+ are Write-Clean.\r
\r
- @param Uhc The UHCI device\r
+ @param Uhc The UHCI device.\r
\r
- @return None\r
+ @return None.\r
\r
**/\r
VOID\r
UhciAckAllInterrupt (\r
IN USB_HC_DEV *Uhc\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
- Stop the host controller\r
+ Stop the host controller.\r
\r
- @param Uhc The UHCI device\r
- @param Timeout Max time allowed\r
+ @param Uhc The UHCI device.\r
+ @param Timeout Max time allowed.\r
\r
- @retval EFI_SUCCESS The host controller is stopped\r
- @retval EFI_TIMEOUT Failed to stop the host controller\r
+ @retval EFI_SUCCESS The host controller is stopped.\r
+ @retval EFI_TIMEOUT Failed to stop the host controller.\r
\r
**/\r
EFI_STATUS\r
UhciStopHc (\r
IN USB_HC_DEV *Uhc,\r
IN UINTN Timeout\r
- )\r
-;\r
+ );\r
\r
\r
\r
/**\r
- Check whether the host controller operates well\r
+ Check whether the host controller operates well.\r
\r
- @param PciIo The PCI_IO protocol to use\r
+ @param PciIo The PCI_IO protocol to use.\r
\r
- @retval TRUE Host controller is working\r
- @retval FALSE Host controller is halted or system error\r
+ @retval TRUE Host controller is working.\r
+ @retval FALSE Host controller is halted or system error.\r
\r
**/\r
BOOLEAN\r
UhciIsHcWorking (\r
IN EFI_PCI_IO_PROTOCOL *PciIo\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
Set the UHCI frame list base address. It can't use\r
UhciWriteReg which access memory in UINT16.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL to use\r
- @param Addr Address to set\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r
+ @param Addr Address to set.\r
\r
- @return VOID\r
+ @return None.\r
\r
**/\r
VOID\r
UhciSetFrameListBaseAddr (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN VOID *Addr\r
- )\r
-;\r
+ );\r
\r
\r
/**\r
- Disable USB Emulation\r
+ Disable USB Emulation.\r
\r
- @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use\r
+ @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r
\r
- @return VOID\r
+ @return None.\r
\r
**/\r
VOID\r
UhciTurnOffUsbEmulation (\r
IN EFI_PCI_IO_PROTOCOL *PciIo\r
- )\r
-;\r
+ );\r
#endif\r
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