MdeModulePkg: Misc comments and DEBUG messages

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciSched.c

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
index 0d97bccabadd52c6b84da016a8d48210a9416348..90f010c9985ba0d9b8559f889be9e94d60529135 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
@@ -2,7 +2,7 @@
 \r
   The EHCI register operation routines.\r
 \r
-Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -519,7 +519,7 @@ UhciCheckTdStatus (
       // terminate the transfer\r
       //\r
       if (!IsLow && (TdHw->ShortPacket == 1) && (Len < Td->DataLen)) {\r
-        DEBUG ((EFI_D_INFO, "UhciCheckTdStatus: short packet read occured\n"));\r
+        DEBUG ((EFI_D_VERBOSE, "UhciCheckTdStatus: short packet read occured\n"));\r
 \r
         Finished = TRUE;\r
         goto ON_EXIT;\r
@@ -580,7 +580,7 @@ UhciExecuteTransfer (
 \r
   Finished     = FALSE;\r
   Status       = EFI_SUCCESS;\r
-  Delay        = (TimeOut * UHC_1_MILLISECOND / UHC_SYNC_POLL_INTERVAL) + 1;\r
+  Delay        = TimeOut * UHC_1_MILLISECOND;\r
   InfiniteLoop = FALSE;\r
 \r
   //\r
@@ -602,7 +602,7 @@ UhciExecuteTransfer (
       break;\r
     }\r
 \r
-    gBS->Stall (UHC_SYNC_POLL_INTERVAL);\r
+    gBS->Stall (UHC_1_MICROSECOND);\r
   }\r
 \r
   if (!Finished) {\r