MdeModulePkg/XhciDxe: Usb legacy support feature is optional. For those usb 3.0 devic...

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index 874967974c87daddd4acf9ea90b3fc3d8d51bb13..a66d7cd95b81829527d6d01b4af5f5418e1dc63e 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -191,39 +191,6 @@ XhcWriteOpReg16 (
   }\r
 }\r
 \r
-/**\r
-  Write the data to the 8-bytes width XHCI operational register.\r
-\r
-  @param  Xhc          The XHCI Instance.\r
-  @param  Offset       The offset of the 8-bytes width operational register.\r
-  @param  Data         The data to write.\r
-\r
-**/\r
-VOID\r
-XhcWriteOpReg64 (\r
-  IN USB_XHCI_INSTANCE    *Xhc,\r
-  IN UINT32               Offset,\r
-  IN UINT64               Data\r
-  )\r
-{\r
-  EFI_STATUS              Status;\r
-\r
-  ASSERT (Xhc->CapLength != 0);\r
-\r
-  Status = Xhc->PciIo->Mem.Write (\r
-                             Xhc->PciIo,\r
-                             EfiPciIoWidthUint64,\r
-                             XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->CapLength + Offset),\r
-                             1,\r
-                             &Data\r
-                             );\r
-\r
-  if (EFI_ERROR (Status)) {\r
-    DEBUG ((EFI_D_ERROR, "XhcWriteOpReg64: Pci Io Write error: %r at %d\n", Status, Offset));\r
-  }\r
-}\r
-\r
 /**\r
   Read XHCI door bell register.\r
 \r
@@ -331,43 +298,6 @@ XhcReadRuntimeReg (
   return Data;\r
 }\r
 \r
-/**\r
-  Read 8-bytes width XHCI runtime register.\r
-\r
-  @param  Xhc          The XHCI Instance.\r
-  @param  Offset       The offset of the 8-bytes width runtime register.\r
-\r
-  @return The register content read\r
-\r
-**/\r
-UINT64\r
-XhcReadRuntimeReg64 (\r
-  IN  USB_XHCI_INSTANCE   *Xhc,\r
-  IN  UINT32              Offset\r
-  )\r
-{\r
-  UINT64                  Data;\r
-  EFI_STATUS              Status;\r
-\r
-  ASSERT (Xhc->RTSOff != 0);\r
-\r
-  Status = Xhc->PciIo->Mem.Read (\r
-                             Xhc->PciIo,\r
-                             EfiPciIoWidthUint64,\r
-                             XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->RTSOff + Offset),\r
-                             1,\r
-                             &Data\r
-                             );\r
-\r
-  if (EFI_ERROR (Status)) {\r
-    DEBUG ((EFI_D_ERROR, "XhcReadRuntimeReg64: Pci Io Read error - %r at %d\n", Status, Offset));\r
-    Data = 0xFFFFFFFFFFFFFFFFULL;\r
-  }\r
-\r
-  return Data;\r
-}\r
-\r
 /**\r
   Write the data to the XHCI runtime register.\r
 \r
@@ -401,39 +331,6 @@ XhcWriteRuntimeReg (
   }\r
 }\r
 \r
-/**\r
-  Write the data to the 8-bytes width XHCI runtime register.\r
-\r
-  @param  Xhc          The XHCI Instance.\r
-  @param  Offset       The offset of the 8-bytes width runtime register.\r
-  @param  Data         The data to write.\r
-\r
-**/\r
-VOID\r
-XhcWriteRuntimeReg64 (\r
-  IN USB_XHCI_INSTANCE    *Xhc,\r
-  IN UINT32               Offset,\r
-  IN UINT64               Data\r
-  )\r
-{\r
-  EFI_STATUS              Status;\r
-\r
-  ASSERT (Xhc->RTSOff != 0);\r
-\r
-  Status = Xhc->PciIo->Mem.Write (\r
-                             Xhc->PciIo,\r
-                             EfiPciIoWidthUint64,\r
-                             XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->RTSOff + Offset),\r
-                             1,\r
-                             &Data\r
-                             );\r
-\r
-  if (EFI_ERROR (Status)) {\r
-    DEBUG ((EFI_D_ERROR, "XhcWriteRuntimeReg64: Pci Io Write error: %r at %d\n", Status, Offset));\r
-  }\r
-}\r
-\r
 /**\r
   Read XHCI extended capability register.\r
 \r
@@ -646,6 +543,10 @@ XhcSetBiosOwnership (
 {\r
   UINT32                    Buffer;\r
 \r
+  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
+    return;\r
+  }\r
+\r
   DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));\r
 \r
   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
@@ -666,6 +567,10 @@ XhcClearBiosOwnership (
 {\r
   UINT32                    Buffer;\r
 \r
+  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
+    return;\r
+  }\r
+\r
   DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));\r
 \r
   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
@@ -674,16 +579,18 @@ XhcClearBiosOwnership (
 }\r
 \r
 /**\r
-  Calculate the XHCI legacy support capability register offset.\r
+  Calculate the offset of the XHCI capability.\r
 \r
   @param  Xhc     The XHCI Instance.\r
+  @param  CapId   The XHCI Capability ID.\r
 \r
   @return The offset of XHCI legacy support capability register.\r
 \r
 **/\r
 UINT32\r
-XhcGetLegSupCapAddr (\r
-  IN USB_XHCI_INSTANCE    *Xhc\r
+XhcGetCapabilityAddr (\r
+  IN USB_XHCI_INSTANCE    *Xhc,\r
+  IN UINT8                CapId\r
   )\r
 {\r
   UINT32 ExtCapOffset;\r
@@ -697,7 +604,7 @@ XhcGetLegSupCapAddr (
     // Check if the extended capability register's capability id is USB Legacy Support.\r
     //\r
     Data = XhcReadExtCapReg (Xhc, ExtCapOffset);\r
-    if ((Data & 0xFF) == 0x1) {\r
+    if ((Data & 0xFF) == CapId) {\r
       return ExtCapOffset;\r
     }\r
     //\r
@@ -707,7 +614,7 @@ XhcGetLegSupCapAddr (
     ExtCapOffset += (NextExtCapReg << 2);\r
   } while (NextExtCapReg != 0);\r
 \r
-  return 0;\r
+  return 0xFFFFFFFF;\r
 }\r
 \r
 /**\r
@@ -763,6 +670,8 @@ XhcResetHC (
 {\r
   EFI_STATUS              Status;\r
 \r
+  Status = EFI_SUCCESS;\r
+\r
   DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));\r
   //\r
   // Host can only be reset when it is halt. If not so, halt it\r
@@ -775,8 +684,12 @@ XhcResetHC (
     }\r
   }\r
 \r
-  XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
-  Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+  if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
+      ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {\r
+    XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
+    Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+  }\r
+\r
   return Status;\r
 }\r
 \r