\r
This file contains the register definition of XHCI host controller.\r
\r
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define USB_HUB_CLASS_CODE 0x09\r
#define USB_HUB_SUBCLASS_CODE 0x00\r
\r
+#define XHC_CAP_USB_LEGACY 0x01\r
+#define XHC_CAP_USB_DEBUG 0x0A\r
+\r
//============================================//\r
// XHCI register offset //\r
//============================================//\r
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
\r
+//\r
+// Debug registers offset\r
+//\r
+#define XHC_DC_DCCTRL 0x20\r
+\r
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
\r
#define XHC_PORTSC_RESET BIT4 // Port Reset\r
#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State\r
#define XHC_PORTSC_PP BIT9 // Port Power\r
-#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
+#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed\r
#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
\r
+#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
+#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
+#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
+#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
+#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
+#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
+#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
+#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
+#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
+#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
\r
#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
\r
+//\r
+// Hub Class Feature Selector for Clear Port Feature Request\r
+// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
+// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
+//\r
+typedef enum {\r
+ Usb3PortBHPortReset = 28,\r
+ Usb3PortBHPortResetChange = 29\r
+} XHC_PORT_FEATURE;\r
+\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
UINT16 UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
+//\r
+// Structure to map the hardware port states to feature selector for clear port feature request.\r
+//\r
+typedef struct {\r
+ UINT32 HwState;\r
+ UINT16 Selector;\r
+} USB_CLEAR_PORT_MAP;\r
+\r
/**\r
Read 1-byte width XHCI capability register.\r
\r
IN UINT16 Data\r
);\r
\r
-/**\r
- Write the data to the 8-bytes width XHCI operational register.\r
-\r
- @param Xhc The XHCI Instance.\r
- @param Offset The offset of the 8-bytes width operational register.\r
- @param Data The data to write.\r
-\r
-**/\r
-VOID\r
-XhcWriteOpReg64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT64 Data\r
- );\r
-\r
/**\r
Read XHCI runtime register.\r
\r
IN UINT32 Offset\r
);\r
\r
-/**\r
- Read 8-bytes width XHCI runtime register.\r
-\r
- @param Xhc The XHCI Instance.\r
- @param Offset The offset of the 8-bytes width runtime register.\r
-\r
- @return The register content read\r
-\r
-**/\r
-UINT64\r
-XhcReadRuntimeReg64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset\r
- );\r
-\r
/**\r
Write the data to the XHCI runtime register.\r
\r
IN UINT32 Data\r
);\r
\r
-/**\r
- Write the data to the 8-bytes width XHCI runtime register.\r
-\r
- @param Xhc The XHCI Instance.\r
- @param Offset The offset of the 8-bytes width runtime register.\r
- @param Data The data to write.\r
-\r
-**/\r
-VOID\r
-XhcWriteRuntimeReg64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT32 Offset,\r
- IN UINT64 Data\r
- );\r
-\r
/**\r
Read XHCI door bell register.\r
\r
@param Offset The offset of the operational register.\r
@param Bit The bit of the register to wait for.\r
@param WaitToSet Wait the bit to set or clear.\r
- @param Timeout The time to wait before abort (in millisecond, ms).\r
+ @param Timeout The time to wait before abort (in microsecond, us).\r
\r
@retval EFI_SUCCESS The bit successfully changed by host controller.\r
@retval EFI_TIMEOUT The time out occurred.\r
IN UINT32 Bit\r
);\r
\r
+/**\r
+ Read XHCI extended capability register.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param Offset The offset of the extended capability register.\r
+\r
+ @return The register content read\r
+\r
+**/\r
+UINT32\r
+XhcReadExtCapReg (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
+ );\r
+\r
/**\r
Whether the XHCI host controller is halted.\r
\r
Reset the XHCI host controller.\r
\r
@param Xhc The XHCI Instance.\r
- @param Timeout Time to wait before abort (in millisecond, ms).\r
+ @param Timeout Time to wait before abort (in microsecond, us).\r
\r
@retval EFI_SUCCESS The XHCI host controller is reset.\r
@return Others Failed to reset the XHCI before Timeout.\r
Halt the XHCI host controller.\r
\r
@param Xhc The XHCI Instance.\r
- @param Timeout Time to wait before abort (in millisecond, ms).\r
+ @param Timeout Time to wait before abort (in microsecond, us).\r
\r
@return EFI_SUCCESS The XHCI host controller is halt.\r
@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r
Set the XHCI host controller to run.\r
\r
@param Xhc The XHCI Instance.\r
- @param Timeout Time to wait before abort (in millisecond, ms).\r
+ @param Timeout Time to wait before abort (in microsecond, us).\r
\r
@return EFI_SUCCESS The XHCI host controller is running.\r
@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r
);\r
\r
/**\r
- Calculate the XHCI legacy support capability register offset.\r
+ Calculate the offset of the XHCI capability.\r
\r
@param Xhc The XHCI Instance.\r
+ @param CapId The XHCI Capability ID.\r
\r
@return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
-XhcGetLegSupCapAddr (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+XhcGetCapabilityAddr (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 CapId\r
);\r
\r
#endif\r
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