MdeModulePkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
index eea468bbd78026aa85186a3c1db9dd5ffccb7c69..cc5c1bf09a9b20c2ceb6244ffe8b71d5b944bec2 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
@@ -2,14 +2,8 @@
 \r
   This file contains the register definition of XHCI host controller.\r
 \r
-Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution.  The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -26,9 +20,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define XHC_PCI_BAR_OFFSET          0x10       // Memory Bar Register Offset\r
 #define XHC_PCI_BAR_MASK            0xFFFF     // Memory Base Address Mask\r
 \r
+#define XHC_PCI_SBRN_OFFSET         0x60       // Serial Bus Release Number Register Offset\r
+\r
 #define USB_HUB_CLASS_CODE          0x09\r
 #define USB_HUB_SUBCLASS_CODE       0x00\r
 \r
+#define XHC_CAP_USB_LEGACY          0x01\r
+#define XHC_CAP_USB_DEBUG           0x0A\r
+\r
 //============================================//\r
 //           XHCI register offset             //\r
 //============================================//\r
@@ -67,6 +66,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset\r
 #define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset\r
 \r
+//\r
+// Debug registers offset\r
+//\r
+#define XHC_DC_DCCTRL                      0x20\r
+\r
 #define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore\r
 #define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore\r
 \r
@@ -181,12 +185,23 @@ typedef union {
 #define XHC_HUB_PORTSC_PEC                 BIT17 // Hub's Port Enabled/Disabled Change\r
 #define XHC_HUB_PORTSC_OCC                 BIT19 // Hub's Over-Current Change\r
 #define XHC_HUB_PORTSC_PRC                 BIT20 // Hub's Port Reset Change\r
+#define XHC_HUB_PORTSC_BHRC                BIT21 // Hub's Port Warm Reset Change\r
 #define XHC_IMAN_IP                        BIT0  // Interrupt Pending\r
 #define XHC_IMAN_IE                        BIT1  // Interrupt Enable\r
 \r
 #define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval\r
 #define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter\r
 \r
+//\r
+//  Hub Class Feature Selector for Clear Port Feature Request\r
+//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
+//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
+//\r
+typedef enum {\r
+  Usb3PortBHPortReset          = 28,\r
+  Usb3PortBHPortResetChange    = 29\r
+} XHC_PORT_FEATURE;\r
+\r
 //\r
 // Structure to map the hardware port states to the\r
 // UEFI's port states.\r
@@ -196,6 +211,14 @@ typedef struct {
   UINT16                  UefiState;\r
 } USB_PORT_STATE_MAP;\r
 \r
+//\r
+// Structure to map the hardware port states to feature selector for clear port feature request.\r
+//\r
+typedef struct {\r
+  UINT32                  HwState;\r
+  UINT16                  Selector;\r
+} USB_CLEAR_PORT_MAP;\r
+\r
 /**\r
   Read 1-byte width XHCI capability register.\r
 \r
@@ -259,20 +282,6 @@ XhcWriteOpReg (
   IN UINT32               Data\r
   );\r
 \r
-/**\r
-  Write the data to the 2-bytes width XHCI operational register.\r
-\r
-  @param  Xhc          The XHCI Instance.\r
-  @param  Offset       The offset of the 2-bytes width operational register.\r
-  @param  Data         The data to write.\r
-\r
-**/\r
-VOID\r
-XhcWriteOpReg16 (\r
-  IN USB_XHCI_INSTANCE    *Xhc,\r
-  IN UINT32               Offset,\r
-  IN UINT16               Data\r
-  );\r
 \r
 /**\r
   Read XHCI runtime register.\r
@@ -304,20 +313,6 @@ XhcWriteRuntimeReg (
   IN UINT32               Data\r
   );\r
 \r
-/**\r
-  Read XHCI door bell register.\r
-\r
-  @param  Xhc          The XHCI Instance.\r
-  @param  Offset       The offset of the door bell register.\r
-\r
-  @return The register content read\r
-\r
-**/\r
-UINT32\r
-XhcReadDoorBellReg (\r
-  IN  USB_XHCI_INSTANCE   *Xhc,\r
-  IN  UINT32              Offset\r
-  );\r
 \r
 /**\r
   Write the data to the XHCI door bell register.\r
@@ -447,6 +442,21 @@ XhcClearRuntimeRegBit (
   IN UINT32               Bit\r
   );\r
 \r
+/**\r
+  Read XHCI extended capability register.\r
+\r
+  @param  Xhc          The XHCI Instance.\r
+  @param  Offset       The offset of the extended capability register.\r
+\r
+  @return The register content read\r
+\r
+**/\r
+UINT32\r
+XhcReadExtCapReg (\r
+  IN  USB_XHCI_INSTANCE   *Xhc,\r
+  IN  UINT32              Offset\r
+  );\r
+\r
 /**\r
   Whether the XHCI host controller is halted.\r
 \r
@@ -524,16 +534,18 @@ XhcRunHC (
   );\r
 \r
 /**\r
-  Calculate the XHCI legacy support capability register offset.\r
+  Calculate the offset of the XHCI capability.\r
 \r
   @param  Xhc     The XHCI Instance.\r
+  @param  CapId   The XHCI Capability ID.\r
 \r
   @return The offset of XHCI legacy support capability register.\r
 \r
 **/\r
 UINT32\r
-XhcGetLegSupCapAddr (\r
-  IN USB_XHCI_INSTANCE    *Xhc\r
+XhcGetCapabilityAddr (\r
+  IN USB_XHCI_INSTANCE    *Xhc,\r
+  IN UINT8                CapId\r
   );\r
 \r
 #endif\r