\r
XHCI transfer scheduling routines.\r
\r
-Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2011 - 2020, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) Microsoft Corporation.<BR>\r
+Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
@return Created URB or NULL.\r
\r
**/\r
-URB*\r
+URB *\r
XhcCreateCmdTrb (\r
IN USB_XHCI_INSTANCE *Xhc,\r
IN TRB_TEMPLATE *CmdTrb\r
)\r
{\r
- URB *Urb;\r
+ URB *Urb;\r
\r
Urb = AllocateZeroPool (sizeof (URB));\r
if (Urb == NULL) {\r
return NULL;\r
}\r
\r
- Urb->Signature = XHC_URB_SIG;\r
+ Urb->Signature = XHC_URB_SIG;\r
\r
- Urb->Ring = &Xhc->CmdRing;\r
+ Urb->Ring = &Xhc->CmdRing;\r
XhcSyncTrsRing (Xhc, Urb->Ring);\r
- Urb->TrbNum = 1;\r
- Urb->TrbStart = Urb->Ring->RingEnqueue;\r
+ Urb->TrbNum = 1;\r
+ Urb->TrbStart = Urb->Ring->RingEnqueue;\r
CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));\r
Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;\r
Urb->TrbEnd = Urb->TrbStart;\r
\r
- Urb->EvtRing = &Xhc->EventRing;\r
- XhcSyncEventRing (Xhc, Urb->EvtRing);\r
- Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;\r
-\r
return Urb;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
XhcCmdTransfer (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN TRB_TEMPLATE *CmdTrb,\r
- IN UINTN Timeout,\r
- OUT TRB_TEMPLATE **EvtTrb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN TRB_TEMPLATE *CmdTrb,\r
+ IN UINTN Timeout,\r
+ OUT TRB_TEMPLATE **EvtTrb\r
)\r
{\r
- EFI_STATUS Status;\r
- URB *Urb;\r
+ EFI_STATUS Status;\r
+ URB *Urb;\r
\r
//\r
// Validate the parameters\r
Status = EFI_DEVICE_ERROR;\r
\r
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
- DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: HC is halted\n"));\r
goto ON_EXIT;\r
}\r
\r
Urb = XhcCreateCmdTrb (Xhc, CmdTrb);\r
\r
if (Urb == NULL) {\r
- DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcCmdTransfer: failed to create URB\n"));\r
Status = EFI_OUT_OF_RESOURCES;\r
goto ON_EXIT;\r
}\r
\r
- ASSERT (Urb->EvtRing == &Xhc->EventRing);\r
-\r
Status = XhcExecTransfer (Xhc, TRUE, Urb, Timeout);\r
- *EvtTrb = Urb->EvtTrbStart;\r
+ *EvtTrb = Urb->EvtTrb;\r
\r
if (Urb->Result == EFI_USB_NOERROR) {\r
Status = EFI_SUCCESS;\r
}\r
\r
- FreePool (Urb);\r
+ XhcFreeUrb (Xhc, Urb);\r
\r
ON_EXIT:\r
return Status;\r
@return Created URB or NULL\r
\r
**/\r
-URB*\r
+URB *\r
XhcCreateUrb (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 BusAddr,\r
- IN UINT8 EpAddr,\r
- IN UINT8 DevSpeed,\r
- IN UINTN MaxPacket,\r
- IN UINTN Type,\r
- IN EFI_USB_DEVICE_REQUEST *Request,\r
- IN VOID *Data,\r
- IN UINTN DataLen,\r
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
- IN VOID *Context\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 BusAddr,\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 DevSpeed,\r
+ IN UINTN MaxPacket,\r
+ IN UINTN Type,\r
+ IN EFI_USB_DEVICE_REQUEST *Request,\r
+ IN VOID *Data,\r
+ IN UINTN DataLen,\r
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
+ IN VOID *Context\r
)\r
{\r
- USB_ENDPOINT *Ep;\r
- EFI_STATUS Status;\r
- URB *Urb;\r
+ USB_ENDPOINT *Ep;\r
+ EFI_STATUS Status;\r
+ URB *Urb;\r
\r
Urb = AllocateZeroPool (sizeof (URB));\r
if (Urb == NULL) {\r
\r
Status = XhcCreateTransferTrb (Xhc, Urb);\r
ASSERT_EFI_ERROR (Status);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));\r
+ FreePool (Urb);\r
+ Urb = NULL;\r
+ }\r
\r
return Urb;\r
}\r
\r
+/**\r
+ Free an allocated URB.\r
+\r
+ @param Xhc The XHCI device.\r
+ @param Urb The URB to free.\r
+\r
+**/\r
+VOID\r
+XhcFreeUrb (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
+ )\r
+{\r
+ if ((Xhc == NULL) || (Urb == NULL)) {\r
+ return;\r
+ }\r
+\r
+ if (Urb->DataMap != NULL) {\r
+ Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);\r
+ }\r
+\r
+ FreePool (Urb);\r
+}\r
+\r
/**\r
Create a transfer TRB.\r
\r
**/\r
EFI_STATUS\r
XhcCreateTransferTrb (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- VOID *OutputContext;\r
- TRANSFER_RING *EPRing;\r
- UINT8 EPType;\r
- UINT8 SlotId;\r
- UINT8 Dci;\r
- TRB *TrbStart;\r
- UINTN TotalLen;\r
- UINTN Len;\r
- UINTN TrbNum;\r
+ VOID *OutputContext;\r
+ TRANSFER_RING *EPRing;\r
+ UINT8 EPType;\r
+ UINT8 SlotId;\r
+ UINT8 Dci;\r
+ TRB *TrbStart;\r
+ UINTN TotalLen;\r
+ UINTN Len;\r
+ UINTN TrbNum;\r
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ VOID *Map;\r
+ EFI_STATUS Status;\r
\r
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
if (SlotId == 0) {\r
return EFI_DEVICE_ERROR;\r
}\r
\r
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
+ Urb->Finished = FALSE;\r
+ Urb->StartDone = FALSE;\r
+ Urb->EndDone = FALSE;\r
+ Urb->Completed = 0;\r
+ Urb->Result = EFI_USB_NOERROR;\r
+\r
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
ASSERT (Dci < 32);\r
- EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r
- Urb->Ring = EPRing;\r
- OutputContext = (VOID *)(UINTN)Xhc->DCBAA[SlotId];\r
+ EPRing = (TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r
+ Urb->Ring = EPRing;\r
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
if (Xhc->HcCParams.Data.Csz == 0) {\r
- EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r
+ EPType = (UINT8)((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r
} else {\r
- EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r
+ EPType = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r
+ }\r
+\r
+ //\r
+ // No need to remap.\r
+ //\r
+ if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {\r
+ if (((UINT8)(Urb->Ep.Direction)) == EfiUsbDataIn) {\r
+ MapOp = EfiPciIoOperationBusMasterWrite;\r
+ } else {\r
+ MapOp = EfiPciIoOperationBusMasterRead;\r
+ }\r
+\r
+ Len = Urb->DataLen;\r
+ Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r
+\r
+ if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);\r
+ Urb->DataMap = Map;\r
}\r
\r
//\r
Urb->TrbStart = EPRing->RingEnqueue;\r
switch (EPType) {\r
case ED_CONTROL_BIDIR:\r
- Urb->EvtRing = &Xhc->EventRing;\r
- XhcSyncEventRing (Xhc, Urb->EvtRing);\r
- Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;\r
//\r
// For control transfer, create SETUP_STAGE_TRB first.\r
//\r
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;\r
TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;\r
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;\r
TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;\r
TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;\r
- TrbStart->TrbCtrSetup.Lenth = 8;\r
+ TrbStart->TrbCtrSetup.Length = 8;\r
TrbStart->TrbCtrSetup.IntTarget = 0;\r
TrbStart->TrbCtrSetup.IOC = 1;\r
TrbStart->TrbCtrSetup.IDT = 1;\r
TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;\r
- if (Urb->Ep.Direction == EfiUsbDataIn) {\r
- TrbStart->TrbCtrSetup.TRT = 3;\r
- } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
- TrbStart->TrbCtrSetup.TRT = 2;\r
+ if (Urb->DataLen > 0) {\r
+ if (Urb->Ep.Direction == EfiUsbDataIn) {\r
+ TrbStart->TrbCtrSetup.TRT = 3;\r
+ } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
+ TrbStart->TrbCtrSetup.TRT = 2;\r
+ } else {\r
+ DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n"));\r
+ ASSERT (FALSE);\r
+ }\r
} else {\r
TrbStart->TrbCtrSetup.TRT = 0;\r
}\r
+\r
//\r
// Update the cycle bit\r
//\r
//\r
if (Urb->DataLen > 0) {\r
XhcSyncTrsRing (Xhc, EPRing);\r
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
- TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->Data);\r
- TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->Data);\r
- TrbStart->TrbCtrData.Lenth = (UINT32) Urb->DataLen;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
+ TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);\r
+ TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);\r
+ TrbStart->TrbCtrData.Length = (UINT32)Urb->DataLen;\r
TrbStart->TrbCtrData.TDSize = 0;\r
TrbStart->TrbCtrData.IntTarget = 0;\r
TrbStart->TrbCtrData.ISP = 1;\r
} else {\r
TrbStart->TrbCtrData.DIR = 0;\r
}\r
+\r
//\r
// Update the cycle bit\r
//\r
TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;\r
Urb->TrbNum++;\r
}\r
+\r
//\r
// For control transfer, create STATUS_STAGE_TRB.\r
// Get the pointer to next TRB for status stage use\r
//\r
XhcSyncTrsRing (Xhc, EPRing);\r
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
TrbStart->TrbCtrStatus.IntTarget = 0;\r
TrbStart->TrbCtrStatus.IOC = 1;\r
TrbStart->TrbCtrStatus.CH = 0;\r
} else {\r
TrbStart->TrbCtrStatus.DIR = 0;\r
}\r
+\r
//\r
// Update the cycle bit\r
//\r
\r
case ED_BULK_OUT:\r
case ED_BULK_IN:\r
- Urb->EvtRing = &Xhc->EventRing;\r
- XhcSyncEventRing (Xhc, Urb->EvtRing);\r
- Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;\r
-\r
TotalLen = 0;\r
Len = 0;\r
TrbNum = 0;\r
} else {\r
Len = 0x10000;\r
}\r
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);\r
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);\r
- TrbStart->TrbNormal.Lenth = (UINT32) Len;\r
+\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.Length = (UINT32)Len;\r
TrbStart->TrbNormal.TDSize = 0;\r
TrbStart->TrbNormal.IntTarget = 0;\r
TrbStart->TrbNormal.ISP = 1;\r
\r
case ED_INTERRUPT_OUT:\r
case ED_INTERRUPT_IN:\r
- Urb->EvtRing = &Xhc->EventRing;\r
- XhcSyncEventRing (Xhc, Urb->EvtRing);\r
- Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;\r
-\r
TotalLen = 0;\r
Len = 0;\r
TrbNum = 0;\r
} else {\r
Len = 0x10000;\r
}\r
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);\r
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);\r
- TrbStart->TrbNormal.Lenth = (UINT32) Len;\r
+\r
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);\r
+ TrbStart->TrbNormal.Length = (UINT32)Len;\r
TrbStart->TrbNormal.TDSize = 0;\r
TrbStart->TrbNormal.IntTarget = 0;\r
TrbStart->TrbNormal.ISP = 1;\r
break;\r
\r
default:\r
- DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));\r
+ DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n", EPType));\r
ASSERT (FALSE);\r
break;\r
}\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Initialize the XHCI host controller for schedule.\r
\r
**/\r
VOID\r
XhcInitSched (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
VOID *Dcbaa;\r
+ EFI_PHYSICAL_ADDRESS DcbaaPhy;\r
UINT64 CmdRing;\r
+ EFI_PHYSICAL_ADDRESS CmdRingPhy;\r
UINTN Entries;\r
UINT32 MaxScratchpadBufs;\r
UINT64 *ScratchBuf;\r
- UINT64 *ScratchEntryBuf;\r
+ EFI_PHYSICAL_ADDRESS ScratchPhy;\r
+ UINT64 *ScratchEntry;\r
+ EFI_PHYSICAL_ADDRESS ScratchEntryPhy;\r
UINT32 Index;\r
+ UINTN *ScratchEntryMap;\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Initialize memory management.\r
+ //\r
+ Xhc->MemPool = UsbHcInitMemPool (Xhc->PciIo);\r
+ ASSERT (Xhc->MemPool != NULL);\r
\r
//\r
// Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)\r
// The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.\r
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.\r
//\r
- Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);\r
- Dcbaa = AllocatePages (EFI_SIZE_TO_PAGES (Entries));\r
+ Entries = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);\r
+ Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries, FALSE);\r
ASSERT (Dcbaa != NULL);\r
ZeroMem (Dcbaa, Entries);\r
\r
Xhc->MaxScratchpadBufs = MaxScratchpadBufs;\r
ASSERT (MaxScratchpadBufs <= 1023);\r
if (MaxScratchpadBufs != 0) {\r
- ScratchBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)), Xhc->PageSize);\r
- ASSERT (ScratchBuf != NULL);\r
+ //\r
+ // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them\r
+ //\r
+ ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);\r
+ ASSERT (ScratchEntryMap != NULL);\r
+ Xhc->ScratchEntryMap = ScratchEntryMap;\r
+\r
+ //\r
+ // Allocate the buffer to record the host address for each entry\r
+ //\r
+ ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);\r
+ ASSERT (ScratchEntry != NULL);\r
+ Xhc->ScratchEntry = ScratchEntry;\r
+\r
+ ScratchPhy = 0;\r
+ Status = UsbHcAllocateAlignedPages (\r
+ Xhc->PciIo,\r
+ EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),\r
+ Xhc->PageSize,\r
+ (VOID **)&ScratchBuf,\r
+ &ScratchPhy,\r
+ &Xhc->ScratchMap\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));\r
Xhc->ScratchBuf = ScratchBuf;\r
\r
+ //\r
+ // Allocate each scratch buffer\r
+ //\r
for (Index = 0; Index < MaxScratchpadBufs; Index++) {\r
- ScratchEntryBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (Xhc->PageSize), Xhc->PageSize);\r
- ASSERT (ScratchEntryBuf != NULL);\r
- ZeroMem (ScratchEntryBuf, Xhc->PageSize);\r
- *ScratchBuf++ = (UINT64)(UINTN)ScratchEntryBuf;\r
+ ScratchEntryPhy = 0;\r
+ Status = UsbHcAllocateAlignedPages (\r
+ Xhc->PciIo,\r
+ EFI_SIZE_TO_PAGES (Xhc->PageSize),\r
+ Xhc->PageSize,\r
+ (VOID **)&ScratchEntry[Index],\r
+ &ScratchEntryPhy,\r
+ (VOID **)&ScratchEntryMap[Index]\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);\r
+ //\r
+ // Fill with the PCI device address\r
+ //\r
+ *ScratchBuf++ = ScratchEntryPhy;\r
}\r
\r
//\r
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the\r
// Device Context Base Address Array points to the Scratchpad Buffer Array.\r
//\r
- *(UINT64 *)Dcbaa = (UINT64)(UINTN)Xhc->ScratchBuf;\r
+ *(UINT64 *)Dcbaa = (UINT64)(UINTN)ScratchPhy;\r
}\r
\r
//\r
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
// So divide it to two 32-bytes width register access.\r
//\r
- XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(Xhc->DCBAA));\r
- XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->DCBAA));\r
- DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));\r
+ DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);\r
+ XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));\r
+ XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));\r
+\r
+ DEBUG ((DEBUG_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));\r
\r
//\r
// Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register\r
// Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.\r
// So we set RCS as inverted PCS init value to let Command Ring empty\r
//\r
- CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;\r
- ASSERT ((CmdRing & 0x3F) == 0);\r
- CmdRing |= XHC_CRCR_RCS;\r
+ CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;\r
+ CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);\r
+ ASSERT ((CmdRingPhy & 0x3F) == 0);\r
+ CmdRingPhy |= XHC_CRCR_RCS;\r
//\r
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
// So divide it to two 32-bytes width register access.\r
//\r
- XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRing));\r
- XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRing));\r
-\r
- DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));\r
+ XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT (CmdRingPhy));\r
+ XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));\r
\r
//\r
// Disable the 'interrupter enable' bit in USB_CMD\r
// Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer\r
//\r
CreateEventRing (Xhc, &Xhc->EventRing);\r
- DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",\r
+ Xhc->CmdRing.RingSeg0,\r
+ (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,\r
+ Xhc->EventRing.EventRingSeg0,\r
+ (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER\r
+ ));\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcRecoverHaltedEndpoint (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- EFI_STATUS Status;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- CMD_TRB_RESET_ENDPOINT CmdTrbResetED;\r
- CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;\r
- UINT8 Dci;\r
- UINT8 SlotId;\r
+ EFI_STATUS Status;\r
+ UINT8 Dci;\r
+ UINT8 SlotId;\r
\r
Status = EFI_SUCCESS;\r
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
if (SlotId == 0) {\r
return EFI_DEVICE_ERROR;\r
}\r
+\r
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
ASSERT (Dci < 32);\r
- \r
- DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));\r
+\r
+ DEBUG ((DEBUG_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));\r
\r
//\r
// 1) Send Reset endpoint command to transit from halt to stop state\r
//\r
- ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));\r
- CmdTrbResetED.CycleBit = 1;\r
- CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;\r
- CmdTrbResetED.EDID = Dci;\r
- CmdTrbResetED.SlotId = SlotId;\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT (!EFI_ERROR(Status));\r
+ Status = XhcResetEndpoint (Xhc, SlotId, Dci);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));\r
+ goto Done;\r
+ }\r
\r
//\r
// 2)Set dequeue pointer\r
//\r
- ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));\r
- CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (Urb->Ring->RingEnqueue) | Urb->Ring->RingPCS;\r
- CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (Urb->Ring->RingEnqueue);\r
- CmdSetTRDeq.CycleBit = 1;\r
- CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;\r
- CmdSetTRDeq.Endpoint = Dci;\r
- CmdSetTRDeq.SlotId = SlotId;\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT (!EFI_ERROR(Status));\r
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));\r
+ goto Done;\r
+ }\r
+\r
+ //\r
+ // 3)Ring the doorbell to transit from stop to active\r
+ //\r
+ XhcRingDoorBell (Xhc, SlotId, Dci);\r
+\r
+Done:\r
+ return Status;\r
+}\r
+\r
+/**\r
+ System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
+ Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
+ the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
+ state.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param Urb The urb which doesn't get completed in a specified timeout range.\r
+\r
+ @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r
+ @retval EFI_ALREADY_STARTED The Urb is finished so no deque is needed.\r
+ @retval Others Failed to stop the endpoint and dequeue the TDs.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcDequeueTrbFromEndpoint (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT8 Dci;\r
+ UINT8 SlotId;\r
+\r
+ Status = EFI_SUCCESS;\r
+ SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
+ if (SlotId == 0) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
+ ASSERT (Dci < 32);\r
+\r
+ DEBUG ((DEBUG_VERBOSE, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));\r
+\r
+ //\r
+ // 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint\r
+ //\r
+ Status = XhcStopEndpoint (Xhc, SlotId, Dci, Urb);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));\r
+ goto Done;\r
+ }\r
+\r
+ //\r
+ // 2)Set dequeue pointer\r
+ //\r
+ if (Urb->Finished && (Urb->Result == EFI_USB_NOERROR)) {\r
+ //\r
+ // Return Already Started to indicate the pending URB is finished.\r
+ // This fixes BULK data loss when transfer is detected as timeout\r
+ // but finished just before stopping endpoint.\r
+ //\r
+ Status = EFI_ALREADY_STARTED;\r
+ DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));\r
+ } else {\r
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));\r
+ goto Done;\r
+ }\r
+ }\r
\r
//\r
// 3)Ring the doorbell to transit from stop to active\r
//\r
XhcRingDoorBell (Xhc, SlotId, Dci);\r
\r
+Done:\r
return Status;\r
}\r
\r
**/\r
VOID\r
CreateEventRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- OUT EVENT_RING *EventRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ OUT EVENT_RING *EventRing\r
)\r
{\r
VOID *Buf;\r
EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;\r
+ UINTN Size;\r
+ EFI_PHYSICAL_ADDRESS ERSTPhy;\r
+ EFI_PHYSICAL_ADDRESS DequeuePhy;\r
\r
ASSERT (EventRing != NULL);\r
\r
- Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));\r
+ Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;\r
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size, TRUE);\r
ASSERT (Buf != NULL);\r
- ASSERT (((UINTN) Buf & 0x3F) == 0);\r
- ZeroMem (Buf, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);\r
+ ASSERT (((UINTN)Buf & 0x3F) == 0);\r
+ ZeroMem (Buf, Size);\r
\r
EventRing->EventRingSeg0 = Buf;\r
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;\r
- EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
- EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
+ EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;\r
+ EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;\r
+\r
+ DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);\r
+\r
//\r
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r
// and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.\r
//\r
EventRing->EventRingCCS = 1;\r
\r
- Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));\r
+ Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;\r
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size, FALSE);\r
ASSERT (Buf != NULL);\r
- ASSERT (((UINTN) Buf & 0x3F) == 0);\r
- ZeroMem (Buf, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);\r
+ ASSERT (((UINTN)Buf & 0x3F) == 0);\r
+ ZeroMem (Buf, Size);\r
\r
- ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;\r
+ ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;\r
EventRing->ERSTBase = ERSTBase;\r
- ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingSeg0);\r
- ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingSeg0);\r
+ ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);\r
+ ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);\r
ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;\r
\r
+ ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);\r
+\r
//\r
// Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)\r
//\r
XhcWriteRuntimeReg (\r
Xhc,\r
XHC_ERDP_OFFSET,\r
- XHC_LOW_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)\r
+ XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)\r
);\r
XhcWriteRuntimeReg (\r
Xhc,\r
XHC_ERDP_OFFSET + 4,\r
- XHC_HIGH_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)\r
+ XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)\r
);\r
//\r
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)\r
XhcWriteRuntimeReg (\r
Xhc,\r
XHC_ERSTBA_OFFSET,\r
- XHC_LOW_32BIT((UINT64)(UINTN)ERSTBase)\r
+ XHC_LOW_32BIT ((UINT64)(UINTN)ERSTPhy)\r
);\r
XhcWriteRuntimeReg (\r
Xhc,\r
XHC_ERSTBA_OFFSET + 4,\r
- XHC_HIGH_32BIT((UINT64)(UINTN)ERSTBase)\r
+ XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTPhy)\r
);\r
//\r
// Need set IMAN IE bit to enble the ring interrupt\r
**/\r
VOID\r
CreateTransferRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINTN TrbNum,\r
- OUT TRANSFER_RING *TransferRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINTN TrbNum,\r
+ OUT TRANSFER_RING *TransferRing\r
)\r
{\r
VOID *Buf;\r
LINK_TRB *EndTrb;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
- Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TrbNum));\r
+ Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum, TRUE);\r
ASSERT (Buf != NULL);\r
- ASSERT (((UINTN) Buf & 0x3F) == 0);\r
+ ASSERT (((UINTN)Buf & 0x3F) == 0);\r
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
\r
- TransferRing->RingSeg0 = Buf;\r
- TransferRing->TrbNumber = TrbNum;\r
- TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
- TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r
- TransferRing->RingPCS = 1;\r
+ TransferRing->RingSeg0 = Buf;\r
+ TransferRing->TrbNumber = TrbNum;\r
+ TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;\r
+ TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;\r
+ TransferRing->RingPCS = 1;\r
//\r
// 4.9.2 Transfer Ring Management\r
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to\r
// point to the first TRB in the ring.\r
//\r
- EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r
+ EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r
EndTrb->Type = TRB_TYPE_LINK;\r
- EndTrb->PtrLo = XHC_LOW_32BIT (Buf);\r
- EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r
+ EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
//\r
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.\r
//\r
- EndTrb->TC = 1;\r
+ EndTrb->TC = 1;\r
//\r
// Set Cycle bit as other TRB PCS init value\r
//\r
EFI_STATUS\r
EFIAPI\r
XhcFreeEventRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN EVENT_RING *EventRing\r
-)\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN EVENT_RING *EventRing\r
+ )\r
{\r
- UINT8 Index;\r
- EVENT_RING_SEG_TABLE_ENTRY *TablePtr;\r
- VOID *RingBuf;\r
- EVENT_RING_SEG_TABLE_ENTRY *EventRingPtr;\r
-\r
- if(EventRing->EventRingSeg0 == NULL) {\r
+ if (EventRing->EventRingSeg0 == NULL) {\r
return EFI_SUCCESS;\r
}\r
\r
//\r
- // Get the Event Ring Segment Table base address\r
+ // Free EventRing Segment 0\r
//\r
- TablePtr = (EVENT_RING_SEG_TABLE_ENTRY *)(EventRing->ERSTBase);\r
+ UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);\r
\r
//\r
- // Get all the TRBs Ring and release\r
+ // Free ESRT table\r
//\r
- for (Index = 0; Index < ERST_NUMBER; Index++) {\r
- EventRingPtr = TablePtr + Index;\r
- RingBuf = (VOID *)(UINTN)(EventRingPtr->PtrLo | LShiftU64 ((UINT64)EventRingPtr->PtrHi, 32));\r
-\r
- if(RingBuf != NULL) {\r
- FreePages (RingBuf, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));\r
- ZeroMem (EventRingPtr, sizeof (EVENT_RING_SEG_TABLE_ENTRY));\r
- }\r
- }\r
-\r
- FreePages (TablePtr, EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));\r
+ UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
VOID\r
XhcFreeSched (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
- UINT32 Index;\r
- UINT64 *ScratchBuf;\r
+ UINT32 Index;\r
+ UINT64 *ScratchEntry;\r
\r
if (Xhc->ScratchBuf != NULL) {\r
- ScratchBuf = Xhc->ScratchBuf;\r
+ ScratchEntry = Xhc->ScratchEntry;\r
for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {\r
- FreeAlignedPages ((VOID*)(UINTN)*ScratchBuf++, EFI_SIZE_TO_PAGES (Xhc->PageSize));\r
+ //\r
+ // Free Scratchpad Buffers\r
+ //\r
+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *)Xhc->ScratchEntryMap[Index]);\r
}\r
- FreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)));\r
+\r
+ //\r
+ // Free Scratchpad Buffer Array\r
+ //\r
+ UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);\r
+ FreePool (Xhc->ScratchEntryMap);\r
+ FreePool (Xhc->ScratchEntry);\r
+ }\r
+\r
+ if (Xhc->CmdRing.RingSeg0 != NULL) {\r
+ UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);\r
+ Xhc->CmdRing.RingSeg0 = NULL;\r
}\r
\r
+ XhcFreeEventRing (Xhc, &Xhc->EventRing);\r
+\r
if (Xhc->DCBAA != NULL) {\r
- FreePages (Xhc->DCBAA, EFI_SIZE_TO_PAGES((Xhc->MaxSlotsEn + 1) * sizeof(UINT64)));\r
+ UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));\r
Xhc->DCBAA = NULL;\r
}\r
\r
- if (Xhc->CmdRing.RingSeg0 != NULL){\r
- FreePages (Xhc->CmdRing.RingSeg0, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER));\r
- Xhc->CmdRing.RingSeg0 = NULL;\r
+ //\r
+ // Free memory pool at last\r
+ //\r
+ if (Xhc->MemPool != NULL) {\r
+ UsbHcFreeMemPool (Xhc->MemPool);\r
+ Xhc->MemPool = NULL;\r
}\r
-\r
- XhcFreeEventRing (Xhc,&Xhc->EventRing);\r
}\r
\r
/**\r
- Check if it is ring TRB.\r
+ Check if the Trb is a transaction of the URB.\r
\r
- @param Ring The transfer ring\r
- @param Trb The TRB to check if it's in the transfer ring\r
+ @param Xhc The XHCI Instance.\r
+ @param Trb The TRB to be checked\r
+ @param Urb The URB to be checked.\r
\r
- @retval TRUE It is in the ring\r
- @retval FALSE It is not in the ring\r
+ @retval TRUE It is a transaction of the URB.\r
+ @retval FALSE It is not any transaction of the URB.\r
\r
**/\r
BOOLEAN\r
IsTransferRingTrb (\r
- IN TRANSFER_RING *Ring,\r
- IN TRB_TEMPLATE *Trb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN TRB_TEMPLATE *Trb,\r
+ IN URB *Urb\r
)\r
{\r
- BOOLEAN Flag;\r
- TRB_TEMPLATE *Trb1;\r
- UINTN Index;\r
+ LINK_TRB *LinkTrb;\r
+ TRB_TEMPLATE *CheckedTrb;\r
+ UINTN Index;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+\r
+ CheckedTrb = Urb->TrbStart;\r
+ for (Index = 0; Index < Urb->TrbNum; Index++) {\r
+ if (Trb == CheckedTrb) {\r
+ return TRUE;\r
+ }\r
\r
- Trb1 = Ring->RingSeg0;\r
- Flag = FALSE;\r
+ CheckedTrb++;\r
+ //\r
+ // If the checked TRB is the link TRB at the end of the transfer ring,\r
+ // recircle it to the head of the ring.\r
+ //\r
+ if (CheckedTrb->Type == TRB_TYPE_LINK) {\r
+ LinkTrb = (LINK_TRB *)CheckedTrb;\r
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64)LinkTrb->PtrHi, 32));\r
+ CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));\r
+ ASSERT (CheckedTrb == Urb->Ring->RingSeg0);\r
+ }\r
+ }\r
\r
- ASSERT (Ring->TrbNumber == CMD_RING_TRB_NUMBER || Ring->TrbNumber == TR_RING_TRB_NUMBER);\r
+ return FALSE;\r
+}\r
\r
- for (Index = 0; Index < Ring->TrbNumber; Index++) {\r
- if (Trb == Trb1) {\r
- Flag = TRUE;\r
- break;\r
+/**\r
+ Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param Trb The TRB to be checked.\r
+ @param Urb The pointer to the matched Urb.\r
+\r
+ @retval TRUE The Trb is matched with a transaction of the URBs in the async list.\r
+ @retval FALSE The Trb is not matched with any URBs in the async list.\r
+\r
+**/\r
+BOOLEAN\r
+IsAsyncIntTrb (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN TRB_TEMPLATE *Trb,\r
+ OUT URB **Urb\r
+ )\r
+{\r
+ LIST_ENTRY *Entry;\r
+ LIST_ENTRY *Next;\r
+ URB *CheckedUrb;\r
+\r
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
+ CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
+ if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {\r
+ *Urb = CheckedUrb;\r
+ return TRUE;\r
}\r
- Trb1++;\r
}\r
\r
- return Flag;\r
+ return FALSE;\r
}\r
\r
/**\r
@return Whether the result of URB transfer is finialized.\r
\r
**/\r
-EFI_STATUS\r
+BOOLEAN\r
XhcCheckUrbResult (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- BOOLEAN StartDone;\r
- BOOLEAN EndDone;\r
- EVT_TRB_TRANSFER *EvtTrb;\r
- TRB_TEMPLATE *TRBPtr;\r
- UINTN Index;\r
- UINT8 TRBType;\r
- EFI_STATUS Status;\r
+ EVT_TRB_TRANSFER *EvtTrb;\r
+ TRB_TEMPLATE *TRBPtr;\r
+ UINTN Index;\r
+ UINT8 TRBType;\r
+ EFI_STATUS Status;\r
+ URB *AsyncUrb;\r
+ URB *CheckedUrb;\r
+ UINT64 XhcDequeue;\r
+ UINT32 High;\r
+ UINT32 Low;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT ((Xhc != NULL) && (Urb != NULL));\r
\r
- Urb->Completed = 0;\r
- Urb->Result = EFI_USB_NOERROR;\r
- Status = EFI_SUCCESS;\r
- EvtTrb = NULL;\r
+ Status = EFI_SUCCESS;\r
+ AsyncUrb = NULL;\r
+\r
+ if (Urb->Finished) {\r
+ goto EXIT;\r
+ }\r
+\r
+ EvtTrb = NULL;\r
\r
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
Urb->Result |= EFI_USB_ERR_SYSTEM;\r
- Status = EFI_DEVICE_ERROR;\r
goto EXIT;\r
}\r
\r
//\r
- // Restore the EventRingDequeue and poll the transfer event ring from beginning\r
+ // Traverse the event ring to find out all new events from the previous check.\r
//\r
- StartDone = FALSE;\r
- EndDone = FALSE;\r
- Urb->EvtRing->EventRingDequeue = Urb->EvtTrbStart;\r
- for (Index = 0; Index < Urb->EvtRing->TrbNumber; Index++) {\r
- XhcSyncEventRing (Xhc, Urb->EvtRing);\r
- Status = XhcCheckNewEvent (Xhc, Urb->EvtRing, ((TRB_TEMPLATE **)&EvtTrb));\r
+ XhcSyncEventRing (Xhc, &Xhc->EventRing);\r
+ for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {\r
+ Status = XhcCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));\r
if (Status == EFI_NOT_READY) {\r
- Urb->Result |= EFI_USB_ERR_TIMEOUT;\r
+ //\r
+ // All new events are handled, return directly.\r
+ //\r
goto EXIT;\r
}\r
\r
continue;\r
}\r
\r
- TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));\r
- if (IsTransferRingTrb (Urb->Ring, TRBPtr)) {\r
- switch (EvtTrb->Completecode) {\r
- case TRB_COMPLETION_STALL_ERROR:\r
- Urb->Result |= EFI_USB_ERR_STALL;\r
- Status = EFI_DEVICE_ERROR;\r
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r
- goto EXIT;\r
- break;\r
-\r
- case TRB_COMPLETION_BABBLE_ERROR:\r
- Urb->Result |= EFI_USB_ERR_BABBLE;\r
- Status = EFI_DEVICE_ERROR;\r
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r
- goto EXIT;\r
- break;\r
-\r
- case TRB_COMPLETION_DATA_BUFFER_ERROR:\r
- Urb->Result |= EFI_USB_ERR_BUFFER;\r
- Status = EFI_DEVICE_ERROR;\r
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));\r
- goto EXIT;\r
- break;\r
-\r
- case TRB_COMPLETION_USB_TRANSACTION_ERROR:\r
- Urb->Result |= EFI_USB_ERR_TIMEOUT;\r
- Status = EFI_DEVICE_ERROR;\r
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r
- goto EXIT;\r
- break;\r
-\r
- case TRB_COMPLETION_SHORT_PACKET:\r
- case TRB_COMPLETION_SUCCESS:\r
- if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {\r
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: short packet happens!\n"));\r
- }\r
-\r
- TRBType = (UINT8) (TRBPtr->Type);\r
- if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r
- (TRBType == TRB_TYPE_NORMAL) ||\r
- (TRBType == TRB_TYPE_ISOCH)) {\r
- Urb->Completed += (Urb->DataLen - EvtTrb->Lenth);\r
- }\r
-\r
- Status = EFI_SUCCESS;\r
- break;\r
-\r
- default:\r
- DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));\r
- Urb->Result |= EFI_USB_ERR_TIMEOUT;\r
- Status = EFI_DEVICE_ERROR;\r
- goto EXIT;\r
- break;\r
- }\r
+ //\r
+ // Need convert pci device address to host address\r
+ //\r
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));\r
+ TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));\r
\r
- //\r
- // Only check first and end Trb event address\r
- //\r
- if (TRBPtr == Urb->TrbStart) {\r
- StartDone = TRUE;\r
- }\r
+ //\r
+ // Update the status of URB including the pending URB, the URB that is currently checked,\r
+ // and URBs in the XHCI's async interrupt transfer list.\r
+ // This way is used to avoid that those completed async transfer events don't get\r
+ // handled in time and are flushed by newer coming events.\r
+ //\r
+ if ((Xhc->PendingUrb != NULL) && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {\r
+ CheckedUrb = Xhc->PendingUrb;\r
+ } else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {\r
+ CheckedUrb = Urb;\r
+ } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {\r
+ CheckedUrb = AsyncUrb;\r
+ } else {\r
+ continue;\r
+ }\r
\r
- if (TRBPtr == Urb->TrbEnd) {\r
- EndDone = TRUE;\r
- }\r
+ switch (EvtTrb->Completecode) {\r
+ case TRB_COMPLETION_STALL_ERROR:\r
+ CheckedUrb->Result |= EFI_USB_ERR_STALL;\r
+ CheckedUrb->Finished = TRUE;\r
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));\r
+ goto EXIT;\r
+\r
+ case TRB_COMPLETION_BABBLE_ERROR:\r
+ CheckedUrb->Result |= EFI_USB_ERR_BABBLE;\r
+ CheckedUrb->Finished = TRUE;\r
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));\r
+ goto EXIT;\r
+\r
+ case TRB_COMPLETION_DATA_BUFFER_ERROR:\r
+ CheckedUrb->Result |= EFI_USB_ERR_BUFFER;\r
+ CheckedUrb->Finished = TRUE;\r
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));\r
+ goto EXIT;\r
+\r
+ case TRB_COMPLETION_USB_TRANSACTION_ERROR:\r
+ CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r
+ CheckedUrb->Finished = TRUE;\r
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));\r
+ goto EXIT;\r
+\r
+ case TRB_COMPLETION_STOPPED:\r
+ case TRB_COMPLETION_STOPPED_LENGTH_INVALID:\r
+ CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r
+ CheckedUrb->Finished = TRUE;\r
+ //\r
+ // The pending URB is timeout and force stopped when stopping endpoint.\r
+ // Continue the loop to receive the Command Complete Event for stopping endpoint.\r
+ //\r
+ continue;\r
+\r
+ case TRB_COMPLETION_SHORT_PACKET:\r
+ case TRB_COMPLETION_SUCCESS:\r
+ if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {\r
+ DEBUG ((DEBUG_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));\r
+ }\r
+\r
+ TRBType = (UINT8)(TRBPtr->Type);\r
+ if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r
+ (TRBType == TRB_TYPE_NORMAL) ||\r
+ (TRBType == TRB_TYPE_ISOCH))\r
+ {\r
+ CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);\r
+ }\r
\r
- if (StartDone && EndDone) {\r
break;\r
- }\r
+\r
+ default:\r
+ DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));\r
+ CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r
+ CheckedUrb->Finished = TRUE;\r
+ goto EXIT;\r
+ }\r
+\r
+ //\r
+ // Only check first and end Trb event address\r
+ //\r
+ if (TRBPtr == CheckedUrb->TrbStart) {\r
+ CheckedUrb->StartDone = TRUE;\r
+ }\r
+\r
+ if (TRBPtr == CheckedUrb->TrbEnd) {\r
+ CheckedUrb->EndDone = TRUE;\r
+ }\r
+\r
+ if (CheckedUrb->StartDone && CheckedUrb->EndDone) {\r
+ CheckedUrb->Finished = TRUE;\r
+ CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;\r
}\r
}\r
\r
EXIT:\r
- return Status;\r
-}\r
\r
+ //\r
+ // Advance event ring to last available entry\r
+ //\r
+ // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
+ // So divide it to two 32-bytes width register access.\r
+ //\r
+ Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r
+ High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r
+ XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);\r
+\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));\r
+\r
+ if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {\r
+ //\r
+ // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
+ // So divide it to two 32-bytes width register access.\r
+ //\r
+ XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);\r
+ XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));\r
+ }\r
+\r
+ return Urb->Finished;\r
+}\r
\r
/**\r
Execute the transfer by polling the URB. This is a synchronous operation.\r
\r
- @param Xhc The XHCI Instance.\r
- @param CmdTransfer The executed URB is for cmd transfer or not.\r
- @param Urb The URB to execute.\r
- @param Timeout The time to wait before abort, in millisecond.\r
+ @param Xhc The XHCI Instance.\r
+ @param CmdTransfer The executed URB is for cmd transfer or not.\r
+ @param Urb The URB to execute.\r
+ @param Timeout The time to wait before abort, in millisecond.\r
\r
- @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
- @return EFI_TIMEOUT The transfer failed due to time out.\r
- @return EFI_SUCCESS The transfer finished OK.\r
+ @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
+ @return EFI_TIMEOUT The transfer failed due to time out.\r
+ @return EFI_SUCCESS The transfer finished OK.\r
+ @retval EFI_OUT_OF_RESOURCES Memory for the timer event could not be allocated.\r
\r
**/\r
EFI_STATUS\r
XhcExecTransfer (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN BOOLEAN CmdTransfer,\r
- IN URB *Urb,\r
- IN UINTN Timeout\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN BOOLEAN CmdTransfer,\r
+ IN URB *Urb,\r
+ IN UINTN Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINTN Loop;\r
- UINT8 SlotId;\r
- UINT8 Dci;\r
+ EFI_STATUS Status;\r
+ UINT8 SlotId;\r
+ UINT8 Dci;\r
+ BOOLEAN Finished;\r
+ EFI_EVENT TimeoutEvent;\r
+ BOOLEAN IndefiniteTimeout;\r
+\r
+ Status = EFI_SUCCESS;\r
+ Finished = FALSE;\r
+ TimeoutEvent = NULL;\r
+ IndefiniteTimeout = FALSE;\r
\r
if (CmdTransfer) {\r
SlotId = 0;\r
if (SlotId == 0) {\r
return EFI_DEVICE_ERROR;\r
}\r
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
+\r
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
ASSERT (Dci < 32);\r
}\r
\r
- Status = EFI_SUCCESS;\r
- Loop = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;\r
if (Timeout == 0) {\r
- Loop = 0xFFFFFFFF;\r
+ IndefiniteTimeout = TRUE;\r
+ goto RINGDOORBELL;\r
}\r
\r
- XhcRingDoorBell (Xhc, SlotId, Dci);\r
+ Status = gBS->CreateEvent (\r
+ EVT_TIMER,\r
+ TPL_CALLBACK,\r
+ NULL,\r
+ NULL,\r
+ &TimeoutEvent\r
+ );\r
\r
- for (Index = 0; Index < Loop; Index++) {\r
- Status = XhcCheckUrbResult (Xhc, Urb);\r
- if ((Status != EFI_NOT_READY)) {\r
- break;\r
+ if (EFI_ERROR (Status)) {\r
+ goto DONE;\r
+ }\r
+\r
+ Status = gBS->SetTimer (\r
+ TimeoutEvent,\r
+ TimerRelative,\r
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto DONE;\r
+ }\r
+\r
+RINGDOORBELL:\r
+ XhcRingDoorBell (Xhc, SlotId, Dci);\r
+\r
+ do {\r
+ Finished = XhcCheckUrbResult (Xhc, Urb);\r
+ if (Finished) {\r
+ break;\r
}\r
- gBS->Stall (XHC_POLL_DELAY);\r
+\r
+ gBS->Stall (XHC_1_MICROSECOND);\r
+ } while (IndefiniteTimeout || EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));\r
+\r
+DONE:\r
+ if (EFI_ERROR (Status)) {\r
+ Urb->Result = EFI_USB_ERR_NOTEXECUTE;\r
+ } else if (!Finished) {\r
+ Urb->Result = EFI_USB_ERR_TIMEOUT;\r
+ Status = EFI_TIMEOUT;\r
+ } else if (Urb->Result != EFI_USB_NOERROR) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ if (TimeoutEvent != NULL) {\r
+ gBS->CloseEvent (TimeoutEvent);\r
}\r
\r
return Status;\r
**/\r
EFI_STATUS\r
XhciDelAsyncIntTransfer (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 BusAddr,\r
- IN UINT8 EpNum\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 BusAddr,\r
+ IN UINT8 EpNum\r
)\r
{\r
LIST_ENTRY *Entry;\r
LIST_ENTRY *Next;\r
URB *Urb;\r
EFI_USB_DATA_DIRECTION Direction;\r
+ EFI_STATUS Status;\r
\r
Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r
EpNum &= 0x0F;\r
\r
Urb = NULL;\r
\r
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
if ((Urb->Ep.BusAddr == BusAddr) &&\r
(Urb->Ep.EpAddr == EpNum) &&\r
- (Urb->Ep.Direction == Direction)) {\r
+ (Urb->Ep.Direction == Direction))\r
+ {\r
+ //\r
+ // Device doesn't finish the IntTransfer until real data comes\r
+ // So the TRB should be removed as well.\r
+ //\r
+ Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));\r
+ }\r
+\r
RemoveEntryList (&Urb->UrbList);\r
FreePool (Urb->Data);\r
- FreePool (Urb);\r
+ XhcFreeUrb (Xhc, Urb);\r
return EFI_SUCCESS;\r
}\r
}\r
**/\r
VOID\r
XhciDelAllAsyncIntTransfers (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+ IN USB_XHCI_INSTANCE *Xhc\r
)\r
{\r
- LIST_ENTRY *Entry;\r
- LIST_ENTRY *Next;\r
- URB *Urb;\r
+ LIST_ENTRY *Entry;\r
+ LIST_ENTRY *Next;\r
+ URB *Urb;\r
+ EFI_STATUS Status;\r
\r
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
+\r
+ //\r
+ // Device doesn't finish the IntTransfer until real data comes\r
+ // So the TRB should be removed as well.\r
+ //\r
+ Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));\r
+ }\r
+\r
RemoveEntryList (&Urb->UrbList);\r
FreePool (Urb->Data);\r
- FreePool (Urb);\r
+ XhcFreeUrb (Xhc, Urb);\r
+ }\r
+}\r
+\r
+/**\r
+ Insert a single asynchronous interrupt transfer for\r
+ the device and endpoint.\r
+\r
+ @param Xhc The XHCI Instance\r
+ @param BusAddr The logical device address assigned by UsbBus driver\r
+ @param EpAddr Endpoint addrress\r
+ @param DevSpeed The device speed\r
+ @param MaxPacket The max packet length of the endpoint\r
+ @param DataLen The length of data buffer\r
+ @param Callback The function to call when data is transferred\r
+ @param Context The context to the callback\r
+\r
+ @return Created URB or NULL\r
+\r
+**/\r
+URB *\r
+XhciInsertAsyncIntTransfer (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 BusAddr,\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 DevSpeed,\r
+ IN UINTN MaxPacket,\r
+ IN UINTN DataLen,\r
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ VOID *Data;\r
+ URB *Urb;\r
+\r
+ Data = AllocateZeroPool (DataLen);\r
+ if (Data == NULL) {\r
+ DEBUG ((DEBUG_ERROR, "%a: failed to allocate buffer\n", __FUNCTION__));\r
+ return NULL;\r
+ }\r
+\r
+ Urb = XhcCreateUrb (\r
+ Xhc,\r
+ BusAddr,\r
+ EpAddr,\r
+ DevSpeed,\r
+ MaxPacket,\r
+ XHC_INT_TRANSFER_ASYNC,\r
+ NULL,\r
+ Data,\r
+ DataLen,\r
+ Callback,\r
+ Context\r
+ );\r
+ if (Urb == NULL) {\r
+ DEBUG ((DEBUG_ERROR, "%a: failed to create URB\n", __FUNCTION__));\r
+ FreePool (Data);\r
+ return NULL;\r
}\r
+\r
+ //\r
+ // New asynchronous transfer must inserted to the head.\r
+ // Check the comments in XhcMoniteAsyncRequests\r
+ //\r
+ InsertHeadList (&Xhc->AsyncIntTransfers, &Urb->UrbList);\r
+\r
+ return Urb;\r
}\r
\r
/**\r
**/\r
VOID\r
XhcUpdateAsyncRequest (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (Urb->Result == EFI_USB_NOERROR) {\r
Status = XhcCreateTransferTrb (Xhc, Urb);\r
if (EFI_ERROR (Status)) {\r
return;\r
}\r
+\r
Status = RingIntTransferDoorBell (Xhc, Urb);\r
if (EFI_ERROR (Status)) {\r
return;\r
}\r
}\r
\r
+/**\r
+ Flush data from PCI controller specific address to mapped system\r
+ memory address.\r
+\r
+ @param Xhc The XHCI device.\r
+ @param Urb The URB to unmap.\r
+\r
+ @retval EFI_SUCCESS Success to flush data to mapped system memory.\r
+ @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.\r
+\r
+**/\r
+EFI_STATUS\r
+XhcFlushAsyncIntMap (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINTN Len;\r
+ VOID *Map;\r
+\r
+ PciIo = Xhc->PciIo;\r
+ Len = Urb->DataLen;\r
+\r
+ if (Urb->Ep.Direction == EfiUsbDataIn) {\r
+ MapOp = EfiPciIoOperationBusMasterWrite;\r
+ } else {\r
+ MapOp = EfiPciIoOperationBusMasterRead;\r
+ }\r
+\r
+ if (Urb->DataMap != NULL) {\r
+ Status = PciIo->Unmap (PciIo, Urb->DataMap);\r
+ if (EFI_ERROR (Status)) {\r
+ goto ON_ERROR;\r
+ }\r
+ }\r
+\r
+ Urb->DataMap = NULL;\r
+\r
+ Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r
+ if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r
+ goto ON_ERROR;\r
+ }\r
+\r
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);\r
+ Urb->DataMap = Map;\r
+ return EFI_SUCCESS;\r
+\r
+ON_ERROR:\r
+ return EFI_DEVICE_ERROR;\r
+}\r
\r
/**\r
Interrupt transfer periodic check handler.\r
VOID\r
EFIAPI\r
XhcMonitorAsyncRequests (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- LIST_ENTRY *Entry;\r
- LIST_ENTRY *Next;\r
- UINT8 *ProcBuf;\r
- URB *Urb;\r
- UINT8 SlotId;\r
- EFI_STATUS Status;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ LIST_ENTRY *Entry;\r
+ LIST_ENTRY *Next;\r
+ UINT8 *ProcBuf;\r
+ URB *Urb;\r
+ UINT8 SlotId;\r
+ EFI_STATUS Status;\r
+ EFI_TPL OldTpl;\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = (USB_XHCI_INSTANCE*) Context;\r
+ Xhc = (USB_XHCI_INSTANCE *)Context;\r
\r
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
\r
//\r
// Check the result of URB execution. If it is still\r
// active, check the next one.\r
//\r
- Status = XhcCheckUrbResult (Xhc, Urb);\r
+ XhcCheckUrbResult (Xhc, Urb);\r
\r
- if (Status == EFI_NOT_READY) {\r
+ if (!Urb->Finished) {\r
continue;\r
}\r
\r
+ //\r
+ // Flush any PCI posted write transactions from a PCI host\r
+ // bridge to system memory.\r
+ //\r
+ Status = XhcFlushAsyncIntMap (Xhc, Urb);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));\r
+ }\r
+\r
//\r
// Allocate a buffer then copy the transferred data for user.\r
// If failed to allocate the buffer, update the URB for next\r
//\r
ProcBuf = NULL;\r
if (Urb->Result == EFI_USB_NOERROR) {\r
- ASSERT (Urb->Completed <= Urb->DataLen);\r
-\r
- ProcBuf = AllocateZeroPool (Urb->Completed);\r
+ //\r
+ // Make sure the data received from HW is no more than expected.\r
+ //\r
+ if (Urb->Completed <= Urb->DataLen) {\r
+ ProcBuf = AllocateZeroPool (Urb->Completed);\r
+ }\r
\r
if (ProcBuf == NULL) {\r
XhcUpdateAsyncRequest (Xhc, Urb);\r
CopyMem (ProcBuf, Urb->Data, Urb->Completed);\r
}\r
\r
- XhcUpdateAsyncRequest (Xhc, Urb);\r
-\r
//\r
// Leave error recovery to its related device driver. A\r
// common case of the error recovery is to re-submit the\r
// his callback. Some drivers may has a lower TPL restriction.\r
//\r
gBS->RestoreTPL (OldTpl);\r
- (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r
+ (Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
}\r
\r
if (ProcBuf != NULL) {\r
gBS->FreePool (ProcBuf);\r
}\r
+\r
+ XhcUpdateAsyncRequest (Xhc, Urb);\r
}\r
gBS->RestoreTPL (OldTpl);\r
}\r
EFI_STATUS\r
EFIAPI\r
XhcPollPortStatusChange (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT8 Port,\r
- IN EFI_USB_PORT_STATUS *PortState\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT8 Port,\r
+ IN EFI_USB_PORT_STATUS *PortState\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 Speed;\r
- UINT8 SlotId;\r
- USB_DEV_ROUTE RouteChart;\r
+ EFI_STATUS Status;\r
+ UINT8 Speed;\r
+ UINT8 SlotId;\r
+ UINT8 Retries;\r
+ USB_DEV_ROUTE RouteChart;\r
\r
- Status = EFI_SUCCESS;\r
+ Status = EFI_SUCCESS;\r
+ Retries = XHC_INIT_DEVICE_SLOT_RETRIES;\r
+\r
+ if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
\r
if (ParentRouteChart.Dword == 0) {\r
RouteChart.Route.RouteString = 0;\r
RouteChart.Route.RootPortNum = Port + 1;\r
RouteChart.Route.TierNum = 1;\r
} else {\r
- if(Port < 14) {\r
+ if (Port < 14) {\r
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
} else {\r
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));\r
}\r
- RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;\r
- RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;\r
+\r
+ RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;\r
+ RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;\r
+ }\r
+\r
+ SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r
+ if (SlotId != 0) {\r
+ if (Xhc->HcCParams.Data.Csz == 0) {\r
+ Status = XhcDisableSlotCmd (Xhc, SlotId);\r
+ } else {\r
+ Status = XhcDisableSlotCmd64 (Xhc, SlotId);\r
+ }\r
}\r
\r
if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&\r
- ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {\r
+ ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0))\r
+ {\r
//\r
// Has a device attached, Identify device speed after port is enabled.\r
//\r
} else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {\r
Speed = EFI_USB_SPEED_SUPER;\r
}\r
- //\r
- // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.\r
- //\r
- SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r
- if (SlotId == 0) {\r
- if (Xhc->HcCParams.Data.Csz == 0) {\r
- Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
- } else {\r
- Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
- }\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
- } else if ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) == 0) {\r
- //\r
- // Device is detached. Disable the allocated device slot and release resource.\r
- //\r
- SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r
- if (SlotId != 0) {\r
- if (Xhc->HcCParams.Data.Csz == 0) {\r
- Status = XhcDisableSlotCmd (Xhc, SlotId);\r
- } else {\r
- Status = XhcDisableSlotCmd64 (Xhc, SlotId);\r
+\r
+ do {\r
+ //\r
+ // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.\r
+ //\r
+ SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r
+ if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {\r
+ if (Xhc->HcCParams.Data.Csz == 0) {\r
+ Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
+ } else {\r
+ Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
+ }\r
}\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
+\r
+ //\r
+ // According to the xHCI specification (section 4.6.5), "a USB Transaction\r
+ // Error Completion Code for an Address Device Command may be due to a Stall\r
+ // response from a device. Software should issue a Disable Slot Command for\r
+ // the Device Slot then an Enable Slot Command to recover from this error."\r
+ // Therefore, retry the device slot initialization if it fails due to a\r
+ // device error.\r
+ //\r
+ } while ((Status == EFI_DEVICE_ERROR) && (Retries-- != 0));\r
}\r
+\r
return Status;\r
}\r
\r
-\r
/**\r
Calculate the device context index by endpoint address and direction.\r
\r
**/\r
UINT8\r
XhcEndpointToDci (\r
- IN UINT8 EpAddr,\r
- IN UINT8 Direction\r
+ IN UINT8 EpAddr,\r
+ IN UINT8 Direction\r
)\r
{\r
- UINT8 Index;\r
+ UINT8 Index;\r
\r
if (EpAddr == 0) {\r
return 1;\r
} else {\r
- Index = (UINT8) (2 * EpAddr);\r
+ Index = (UINT8)(2 * EpAddr);\r
if (Direction == EfiUsbDataIn) {\r
Index += 1;\r
}\r
+\r
return Index;\r
}\r
}\r
for (Index = 0; Index < 255; Index++) {\r
if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {\r
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr))\r
+ {\r
break;\r
}\r
}\r
for (Index = 0; Index < 255; Index++) {\r
if (Xhc->UsbDevContext[Index + 1].Enabled &&\r
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r
- (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {\r
+ (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword))\r
+ {\r
break;\r
}\r
}\r
EFI_STATUS\r
EFIAPI\r
XhcSyncEventRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN EVENT_RING *EvtRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN EVENT_RING *EvtRing\r
)\r
{\r
- UINTN Index;\r
- TRB_TEMPLATE *EvtTrb1;\r
- TRB_TEMPLATE *EvtTrb2;\r
- UINT64 XhcDequeue;\r
- UINT32 High;\r
- UINT32 Low;\r
+ UINTN Index;\r
+ TRB_TEMPLATE *EvtTrb1;\r
\r
ASSERT (EvtRing != NULL);\r
\r
// Calculate the EventRingEnqueue and EventRingCCS.\r
// Note: only support single Segment\r
//\r
- EvtTrb1 = EvtRing->EventRingSeg0;\r
- EvtTrb2 = EvtRing->EventRingSeg0;\r
+ EvtTrb1 = EvtRing->EventRingDequeue;\r
\r
for (Index = 0; Index < EvtRing->TrbNumber; Index++) {\r
- if (EvtTrb1->CycleBit != EvtTrb2->CycleBit) {\r
+ if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {\r
break;\r
}\r
+\r
EvtTrb1++;\r
+\r
+ if ((UINTN)EvtTrb1 >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
+ EvtTrb1 = EvtRing->EventRingSeg0;\r
+ EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;\r
+ }\r
}\r
\r
if (Index < EvtRing->TrbNumber) {\r
EvtRing->EventRingEnqueue = EvtTrb1;\r
- EvtRing->EventRingCCS = (EvtTrb2->CycleBit) ? 1 : 0;\r
} else {\r
- EvtRing->EventRingEnqueue = EvtTrb2;\r
- EvtRing->EventRingCCS = (EvtTrb2->CycleBit) ? 0 : 1;\r
- }\r
-\r
- //\r
- // Apply the EventRingDequeue to Xhc\r
- //\r
- // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
- // So divide it to two 32-bytes width register access.\r
- //\r
- Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r
- High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r
- XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);\r
-\r
- if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)EvtRing->EventRingDequeue & (~0x0F))) {\r
- //\r
- // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r
- // So divide it to two 32-bytes width register access.\r
- //\r
- XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (EvtRing->EventRingDequeue) | BIT3);\r
- XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (EvtRing->EventRingDequeue));\r
+ ASSERT (FALSE);\r
}\r
\r
return EFI_SUCCESS;\r
EFI_STATUS\r
EFIAPI\r
XhcSyncTrsRing (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN TRANSFER_RING *TrsRing\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN TRANSFER_RING *TrsRing\r
)\r
{\r
- UINTN Index;\r
- TRB_TEMPLATE *TrsTrb;\r
+ UINTN Index;\r
+ TRB_TEMPLATE *TrsTrb;\r
\r
ASSERT (TrsRing != NULL);\r
//\r
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {\r
break;\r
}\r
+\r
TrsTrb++;\r
- if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {\r
- ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);\r
+ if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {\r
+ ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);\r
//\r
// set cycle bit in Link TRB as normal\r
//\r
- ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r
+ ((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r
//\r
// Toggle PCS maintained by software\r
//\r
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;\r
- TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);\r
+ TrsTrb = (TRB_TEMPLATE *)TrsRing->RingSeg0; // Use host address\r
}\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
XhcCheckNewEvent (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN EVENT_RING *EvtRing,\r
- OUT TRB_TEMPLATE **NewEvtTrb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN EVENT_RING *EvtRing,\r
+ OUT TRB_TEMPLATE **NewEvtTrb\r
)\r
{\r
- EFI_STATUS Status;\r
- TRB_TEMPLATE*EvtTrb;\r
-\r
ASSERT (EvtRing != NULL);\r
\r
- EvtTrb = EvtRing->EventRingDequeue;\r
*NewEvtTrb = EvtRing->EventRingDequeue;\r
\r
if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {\r
return EFI_NOT_READY;\r
}\r
\r
- Status = EFI_SUCCESS;\r
-\r
- if (((EvtTrb->Status >> 24) & 0xFF) != TRB_COMPLETION_SUCCESS) {\r
- Status = EFI_DEVICE_ERROR;\r
- }\r
-\r
EvtRing->EventRingDequeue++;\r
//\r
// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.\r
//\r
- if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
+ if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;\r
}\r
\r
- return Status;\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcRingDoorBell (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 Dci\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
)\r
{\r
if (SlotId == 0) {\r
**/\r
EFI_STATUS\r
RingIntTransferDoorBell (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN URB *Urb\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN URB *Urb\r
)\r
{\r
- UINT8 SlotId;\r
- UINT8 Dci;\r
+ UINT8 SlotId;\r
+ UINT8 Dci;\r
\r
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
EFI_STATUS\r
EFIAPI\r
XhcInitializeDeviceSlot (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT16 ParentPort,\r
- IN USB_DEV_ROUTE RouteChart,\r
- IN UINT8 DeviceSpeed\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT16 ParentPort,\r
+ IN USB_DEV_ROUTE RouteChart,\r
+ IN UINT8 DeviceSpeed\r
)\r
{\r
EFI_STATUS Status;\r
UINT8 SlotId;\r
UINT8 ParentSlotId;\r
DEVICE_CONTEXT *ParentDeviceContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
CmdTrb.CycleBit = 1;\r
CmdTrb.Type = TRB_TYPE_EN_SLOT;\r
\r
Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));\r
+ return Status;\r
+ }\r
+\r
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
- DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
+ DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
SlotId = (UINT8)EvtTrb->SlotId;\r
ASSERT (SlotId != 0);\r
\r
// 4.3.3 Device Slot Initialization\r
// 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r
//\r
- InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));\r
+ InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT), FALSE);\r
ASSERT (InputContext != NULL);\r
- ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);\r
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
\r
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;\r
\r
//\r
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
//\r
// The device is behind of hub device.\r
//\r
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);\r
ASSERT (ParentSlotId != 0);\r
//\r
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
//\r
ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))\r
+ {\r
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
//\r
// Full/Low device attached to High speed hub port that isolates the high speed signaling\r
//\r
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
//\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
//\r
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
//\r
} else {\r
InputContext->EP[0].MaxPacketSize = 8;\r
}\r
+\r
//\r
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
// 1KB, and Bulk and Isoch endpoints 3KB.\r
//\r
// Init the DCS(dequeue cycle state) as the transfer ring's CCS\r
//\r
- InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;\r
- InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (\r
+ Xhc->MemPool,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
+ sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
+ );\r
+ InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r
+ InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
//\r
// 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r
//\r
- OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));\r
+ OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT), FALSE);\r
ASSERT (OutputContext != NULL);\r
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);\r
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));\r
\r
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
// 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r
// a pointer to the Output Device Context data structure (6.2.1).\r
//\r
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));\r
+ //\r
+ // Fill DCBAA with PCI device address\r
+ //\r
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;\r
\r
//\r
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
// Context data structure described above.\r
//\r
+ // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request\r
+ // to device.\r
+ //\r
+ gBS->Stall (XHC_RESET_RECOVERY_DELAY);\r
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
- CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
- CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r
+ CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbAddr.CycleBit = 1;\r
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT (!EFI_ERROR(Status));\r
-\r
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;\r
- DEBUG ((EFI_D_INFO, " Address %d assigned succeefully\n", DeviceAddress));\r
-\r
- Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT *)OutputContext)->Slot.DeviceAddress;\r
+ DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));\r
+ Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
+ } else {\r
+ DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));\r
+ XhcDisableSlotCmd (Xhc, SlotId);\r
+ }\r
\r
return Status;\r
}\r
EFI_STATUS\r
EFIAPI\r
XhcInitializeDeviceSlot64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN USB_DEV_ROUTE ParentRouteChart,\r
- IN UINT16 ParentPort,\r
- IN USB_DEV_ROUTE RouteChart,\r
- IN UINT8 DeviceSpeed\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN USB_DEV_ROUTE ParentRouteChart,\r
+ IN UINT16 ParentPort,\r
+ IN USB_DEV_ROUTE RouteChart,\r
+ IN UINT8 DeviceSpeed\r
)\r
{\r
EFI_STATUS Status;\r
UINT8 SlotId;\r
UINT8 ParentSlotId;\r
DEVICE_CONTEXT_64 *ParentDeviceContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r
CmdTrb.CycleBit = 1;\r
CmdTrb.Type = TRB_TYPE_EN_SLOT;\r
\r
Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));\r
+ return Status;\r
+ }\r
+\r
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r
- DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
+ DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r
SlotId = (UINT8)EvtTrb->SlotId;\r
ASSERT (SlotId != 0);\r
\r
// 4.3.3 Device Slot Initialization\r
// 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r
//\r
- InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));\r
+ InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64), FALSE);\r
ASSERT (InputContext != NULL);\r
- ASSERT (((UINTN) InputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);\r
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
\r
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;\r
\r
//\r
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r
//\r
// The device is behind of hub device.\r
//\r
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);\r
ASSERT (ParentSlotId != 0);\r
//\r
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r
//\r
ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))\r
+ {\r
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r
//\r
// Full/Low device attached to High speed hub port that isolates the high speed signaling\r
//\r
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r
//\r
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r
//\r
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r
//\r
} else {\r
InputContext->EP[0].MaxPacketSize = 8;\r
}\r
+\r
//\r
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r
// 1KB, and Bulk and Isoch endpoints 3KB.\r
//\r
// Init the DCS(dequeue cycle state) as the transfer ring's CCS\r
//\r
- InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;\r
- InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (\r
+ Xhc->MemPool,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r
+ sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
+ );\r
+ InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r
+ InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
\r
//\r
// 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r
//\r
- OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));\r
+ OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64), FALSE);\r
ASSERT (OutputContext != NULL);\r
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);\r
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));\r
\r
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r
// 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r
// a pointer to the Output Device Context data structure (6.2.1).\r
//\r
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));\r
+ //\r
+ // Fill DCBAA with PCI device address\r
+ //\r
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;\r
\r
//\r
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r
// Context data structure described above.\r
//\r
+ // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request\r
+ // to device.\r
+ //\r
+ gBS->Stall (XHC_RESET_RECOVERY_DELAY);\r
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r
- CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
- CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r
+ CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbAddr.CycleBit = 1;\r
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT (!EFI_ERROR(Status));\r
-\r
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;\r
- DEBUG ((EFI_D_INFO, " Address %d assigned succeefully\n", DeviceAddress));\r
-\r
- Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->Slot.DeviceAddress;\r
+ DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));\r
+ Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r
+ } else {\r
+ DEBUG ((DEBUG_ERROR, " Slot %d address not assigned successfully. Status = %r\n", SlotId, Status));\r
+ XhcDisableSlotCmd64 (Xhc, SlotId);\r
+ }\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Disable the specified device slot.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcDisableSlotCmd (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId\r
)\r
{\r
EFI_STATUS Status;\r
for (Index = 0; Index < 255; Index++) {\r
if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))\r
+ {\r
continue;\r
}\r
\r
Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r
\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r
Xhc->UsbDevContext[Index + 1].SlotId = 0;\r
}\r
}\r
//\r
// Construct the disable slot command\r
//\r
- DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r
+ DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));\r
\r
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r
CmdTrbDisSlot.CycleBit = 1;\r
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r
CmdTrbDisSlot.SlotId = SlotId;\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT_EFI_ERROR(Status);\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));\r
+ return Status;\r
+ }\r
+\r
//\r
// Free the slot's device context entry\r
//\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
if (RingSeg != NULL) {\r
- FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));\r
+ UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
}\r
+\r
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r
}\r
}\r
\r
}\r
}\r
\r
+ if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {\r
+ FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);\r
+ }\r
+\r
if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r
- FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));\r
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r
}\r
\r
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
- FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));\r
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));\r
}\r
+\r
//\r
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
EFI_STATUS\r
EFIAPI\r
XhcDisableSlotCmd64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId\r
)\r
{\r
EFI_STATUS Status;\r
for (Index = 0; Index < 255; Index++) {\r
if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))\r
+ {\r
continue;\r
}\r
\r
Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r
\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r
Xhc->UsbDevContext[Index + 1].SlotId = 0;\r
}\r
}\r
//\r
// Construct the disable slot command\r
//\r
- DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r
+ DEBUG ((DEBUG_INFO, "Disable device slot %d!\n", SlotId));\r
\r
ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r
CmdTrbDisSlot.CycleBit = 1;\r
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r
CmdTrbDisSlot.SlotId = SlotId;\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT_EFI_ERROR(Status);\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));\r
+ return Status;\r
+ }\r
+\r
//\r
// Free the slot's device context entry\r
//\r
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r
RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r
if (RingSeg != NULL) {\r
- FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));\r
+ UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
}\r
+\r
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r
}\r
}\r
\r
}\r
}\r
\r
+ if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {\r
+ FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);\r
+ }\r
+\r
if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r
- FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));\r
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r
}\r
\r
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r
- FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));\r
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));\r
}\r
+\r
//\r
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r
return Status;\r
}\r
\r
-\r
/**\r
- Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
+ Initialize endpoint context in input context.\r
\r
- @param Xhc The XHCI Instance.\r
- @param SlotId The slot id to be configured.\r
- @param DeviceSpeed The device's speed.\r
- @param ConfigDesc The pointer to the usb device configuration descriptor.\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param InputContext The pointer to the input context.\r
+ @param IfDesc The pointer to the usb device interface descriptor.\r
\r
- @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
+ @return The maximum device context index of endpoint.\r
\r
**/\r
-EFI_STATUS\r
+UINT8\r
EFIAPI\r
-XhcSetConfigCmd (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+XhcInitializeEndpointContext (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN INPUT_CONTEXT *InputContext,\r
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc\r
)\r
{\r
- EFI_STATUS Status;\r
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
+ UINTN NumEp;\r
+ UINTN EpIndex;\r
+ UINT8 EpAddr;\r
+ UINT8 Direction;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ UINT8 Interval;\r
+ TRANSFER_RING *EndpointTransferRing;\r
\r
- USB_INTERFACE_DESCRIPTOR *IfDesc;\r
- USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
- UINT8 Index;\r
- UINTN NumEp;\r
- UINTN EpIndex;\r
- UINT8 EpAddr;\r
- UINT8 Direction;\r
- UINT8 Dci;\r
- UINT8 MaxDci;\r
- UINT32 PhyAddr;\r
- UINT8 Interval;\r
+ MaxDci = 0;\r
\r
- TRANSFER_RING *EndpointTransferRing;\r
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
- INPUT_CONTEXT *InputContext;\r
- DEVICE_CONTEXT *OutputContext;\r
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- //\r
- // 4.6.6 Configure Endpoint\r
- //\r
- InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
- OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
- ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
- CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r
+ NumEp = IfDesc->NumEndpoints;\r
+ if (NumEp == 0) {\r
+ MaxDci = 1;\r
+ }\r
\r
- ASSERT (ConfigDesc != NULL);\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
+ for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
+ while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ }\r
+\r
+ if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ }\r
+\r
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
+\r
+ Dci = XhcEndpointToDci (EpAddr, Direction);\r
+ ASSERT (Dci < 32);\r
+ if (Dci > MaxDci) {\r
+ MaxDci = Dci;\r
+ }\r
+\r
+ InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
+ InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r
+\r
+ if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
+ //\r
+ // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
+ //\r
+ InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ } else {\r
+ InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ }\r
+\r
+ switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
+ case USB_ENDPOINT_BULK:\r
+ if (Direction == EfiUsbDataIn) {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
+ } else {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
+ }\r
+\r
+ InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
+ if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "Endpoint[%x]: Created BULK ring [%p~%p)\n",\r
+ EpDesc->EndpointAddress,\r
+ EndpointTransferRing->RingSeg0,\r
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r
+ ));\r
+ }\r
+\r
+ break;\r
+ case USB_ENDPOINT_ISO:\r
+ if (Direction == EfiUsbDataIn) {\r
+ InputContext->EP[Dci-1].CErr = 0;\r
+ InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
+ } else {\r
+ InputContext->EP[Dci-1].CErr = 0;\r
+ InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
+ }\r
+\r
+ //\r
+ // Get the bInterval from descriptor and init the the interval field of endpoint context.\r
+ // Refer to XHCI 1.1 spec section 6.2.3.6.\r
+ //\r
+ if (DeviceSpeed == EFI_USB_SPEED_FULL) {\r
+ Interval = EpDesc->Interval;\r
+ ASSERT (Interval >= 1 && Interval <= 16);\r
+ InputContext->EP[Dci-1].Interval = Interval + 2;\r
+ } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
+ Interval = EpDesc->Interval;\r
+ ASSERT (Interval >= 1 && Interval <= 16);\r
+ InputContext->EP[Dci-1].Interval = Interval - 1;\r
+ }\r
+\r
+ //\r
+ // Do not support isochronous transfer now.\r
+ //\r
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ case USB_ENDPOINT_INTERRUPT:\r
+ if (Direction == EfiUsbDataIn) {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
+ } else {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
+ }\r
+\r
+ InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
+ InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
+ //\r
+ // Get the bInterval from descriptor and init the the interval field of endpoint context\r
+ //\r
+ if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
+ Interval = EpDesc->Interval;\r
+ //\r
+ // Calculate through the bInterval field of Endpoint descriptor.\r
+ //\r
+ ASSERT (Interval != 0);\r
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;\r
+ } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
+ Interval = EpDesc->Interval;\r
+ ASSERT (Interval >= 1 && Interval <= 16);\r
+ //\r
+ // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
+ //\r
+ InputContext->EP[Dci-1].Interval = Interval - 1;\r
+ InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
+ InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r
+ InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ }\r
+\r
+ if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "Endpoint[%x]: Created INT ring [%p~%p)\n",\r
+ EpDesc->EndpointAddress,\r
+ EndpointTransferRing->RingSeg0,\r
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r
+ ));\r
+ }\r
+\r
+ break;\r
+\r
+ case USB_ENDPOINT_CONTROL:\r
+ //\r
+ // Do not support control transfer now.\r
+ //\r
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
+ default:\r
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ }\r
+\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (\r
+ Xhc->MemPool,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
+ sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
+ );\r
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
+ InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
+\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ }\r
+\r
+ return MaxDci;\r
+}\r
+\r
+/**\r
+ Initialize endpoint context in input context.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param InputContext The pointer to the input context.\r
+ @param IfDesc The pointer to the usb device interface descriptor.\r
+\r
+ @return The maximum device context index of endpoint.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+XhcInitializeEndpointContext64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN INPUT_CONTEXT_64 *InputContext,\r
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc\r
+ )\r
+{\r
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
+ UINTN NumEp;\r
+ UINTN EpIndex;\r
+ UINT8 EpAddr;\r
+ UINT8 Direction;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ UINT8 Interval;\r
+ TRANSFER_RING *EndpointTransferRing;\r
+\r
+ MaxDci = 0;\r
+\r
+ NumEp = IfDesc->NumEndpoints;\r
+ if (NumEp == 0) {\r
+ MaxDci = 1;\r
+ }\r
+\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
+ for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
+ while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ }\r
+\r
+ if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ }\r
+\r
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
+\r
+ Dci = XhcEndpointToDci (EpAddr, Direction);\r
+ ASSERT (Dci < 32);\r
+ if (Dci > MaxDci) {\r
+ MaxDci = Dci;\r
+ }\r
+\r
+ InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
+ InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r
+\r
+ if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
+ //\r
+ // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
+ //\r
+ InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ } else {\r
+ InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ }\r
+\r
+ switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
+ case USB_ENDPOINT_BULK:\r
+ if (Direction == EfiUsbDataIn) {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
+ } else {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
+ }\r
+\r
+ InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
+ if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "Endpoint64[%x]: Created BULK ring [%p~%p)\n",\r
+ EpDesc->EndpointAddress,\r
+ EndpointTransferRing->RingSeg0,\r
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r
+ ));\r
+ }\r
+\r
+ break;\r
+ case USB_ENDPOINT_ISO:\r
+ if (Direction == EfiUsbDataIn) {\r
+ InputContext->EP[Dci-1].CErr = 0;\r
+ InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
+ } else {\r
+ InputContext->EP[Dci-1].CErr = 0;\r
+ InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
+ }\r
+\r
+ //\r
+ // Get the bInterval from descriptor and init the the interval field of endpoint context.\r
+ // Refer to XHCI 1.1 spec section 6.2.3.6.\r
+ //\r
+ if (DeviceSpeed == EFI_USB_SPEED_FULL) {\r
+ Interval = EpDesc->Interval;\r
+ ASSERT (Interval >= 1 && Interval <= 16);\r
+ InputContext->EP[Dci-1].Interval = Interval + 2;\r
+ } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
+ Interval = EpDesc->Interval;\r
+ ASSERT (Interval >= 1 && Interval <= 16);\r
+ InputContext->EP[Dci-1].Interval = Interval - 1;\r
+ }\r
+\r
+ //\r
+ // Do not support isochronous transfer now.\r
+ //\r
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ case USB_ENDPOINT_INTERRUPT:\r
+ if (Direction == EfiUsbDataIn) {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
+ } else {\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
+ }\r
+\r
+ InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
+ InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
+ //\r
+ // Get the bInterval from descriptor and init the the interval field of endpoint context\r
+ //\r
+ if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
+ Interval = EpDesc->Interval;\r
+ //\r
+ // Calculate through the bInterval field of Endpoint descriptor.\r
+ //\r
+ ASSERT (Interval != 0);\r
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;\r
+ } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
+ Interval = EpDesc->Interval;\r
+ ASSERT (Interval >= 1 && Interval <= 16);\r
+ //\r
+ // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
+ //\r
+ InputContext->EP[Dci-1].Interval = Interval - 1;\r
+ InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
+ InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r
+ InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ InputContext->EP[Dci-1].CErr = 3;\r
+ }\r
+\r
+ if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;\r
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "Endpoint64[%x]: Created INT ring [%p~%p)\n",\r
+ EpDesc->EndpointAddress,\r
+ EndpointTransferRing->RingSeg0,\r
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r
+ ));\r
+ }\r
+\r
+ break;\r
+\r
+ case USB_ENDPOINT_CONTROL:\r
+ //\r
+ // Do not support control transfer now.\r
+ //\r
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
+ default:\r
+ DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ }\r
+\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (\r
+ Xhc->MemPool,\r
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
+ sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
+ );\r
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
+ InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
+\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ }\r
+\r
+ return MaxDci;\r
+}\r
+\r
+/**\r
+ Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param ConfigDesc The pointer to the usb device configuration descriptor.\r
+\r
+ @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetConfigCmd (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ USB_INTERFACE_DESCRIPTOR *IfDesc;\r
+ UINT8 Index;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+\r
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ INPUT_CONTEXT *InputContext;\r
+ DEVICE_CONTEXT *OutputContext;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+\r
+ //\r
+ // 4.6.6 Configure Endpoint\r
+ //\r
+ InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
+ ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
+ CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r
+\r
+ ASSERT (ConfigDesc != NULL);\r
+\r
+ MaxDci = 0;\r
+\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
+ for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
+ while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ }\r
+\r
+ if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ continue;\r
+ }\r
+\r
+ Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);\r
+ if (Dci > MaxDci) {\r
+ MaxDci = Dci;\r
+ }\r
+\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ }\r
+\r
+ InputContext->InputControlContext.Dword2 |= BIT0;\r
+ InputContext->Slot.ContextEntries = MaxDci;\r
+ //\r
+ // configure endpoint\r
+ //\r
+ ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
+ CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.CycleBit = 1;\r
+ CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
+ CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
+ DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));\r
+ } else {\r
+ Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param ConfigDesc The pointer to the usb device configuration descriptor.\r
+\r
+ @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetConfigCmd64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ USB_INTERFACE_DESCRIPTOR *IfDesc;\r
+ UINT8 Index;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+\r
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ INPUT_CONTEXT_64 *InputContext;\r
+ DEVICE_CONTEXT_64 *OutputContext;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+\r
+ //\r
+ // 4.6.6 Configure Endpoint\r
+ //\r
+ InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
+ ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
+ CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));\r
+\r
+ ASSERT (ConfigDesc != NULL);\r
+\r
+ MaxDci = 0;\r
+\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
+ for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
+ while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ }\r
+\r
+ if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ continue;\r
+ }\r
+\r
+ Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);\r
+ if (Dci > MaxDci) {\r
+ MaxDci = Dci;\r
+ }\r
+\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ }\r
+\r
+ InputContext->InputControlContext.Dword2 |= BIT0;\r
+ InputContext->Slot.ContextEntries = MaxDci;\r
+ //\r
+ // configure endpoint\r
+ //\r
+ ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
+ CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.CycleBit = 1;\r
+ CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
+ CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
+ DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));\r
+ } else {\r
+ Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Stop endpoint through XHCI's Stop_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param Dci The device context index of endpoint.\r
+ @param PendingUrb The pending URB to check completion status when stopping the end point.\r
+\r
+ @retval EFI_SUCCESS Stop endpoint successfully.\r
+ @retval Others Failed to stop endpoint.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcStopEndpoint (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci,\r
+ IN URB *PendingUrb OPTIONAL\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ CMD_TRB_STOP_ENDPOINT CmdTrbStopED;\r
+\r
+ DEBUG ((DEBUG_VERBOSE, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));\r
+\r
+ //\r
+ // When XhcCheckUrbResult waits for the Stop_Endpoint completion, it also checks\r
+ // the PendingUrb completion status, because it's possible that the PendingUrb is\r
+ // finished just before stopping the end point, but after the looping check.\r
+ //\r
+ // The PendingUrb could be passed to XhcCmdTransfer to XhcExecTransfer to XhcCheckUrbResult\r
+ // through function parameter, but That will cause every consumer of XhcCmdTransfer,\r
+ // XhcExecTransfer and XhcCheckUrbResult pass a NULL PendingUrb.\r
+ // But actually only XhcCheckUrbResult is aware of the PendingUrb.\r
+ // So we choose to save the PendingUrb into the USB_XHCI_INSTANCE and use it in XhcCheckUrbResult.\r
+ //\r
+ ASSERT (Xhc->PendingUrb == NULL);\r
+ Xhc->PendingUrb = PendingUrb;\r
+ //\r
+ // Reset the URB result from Timeout to NoError.\r
+ // The USB result will be:\r
+ // changed to Timeout when Stop/StopInvalidLength Transfer Event is received, or\r
+ // remain NoError when Success/ShortPacket Transfer Event is received.\r
+ //\r
+ if (PendingUrb != NULL) {\r
+ PendingUrb->Result = EFI_USB_NOERROR;\r
+ }\r
+\r
+ //\r
+ // Send stop endpoint command to transit Endpoint from running to stop state\r
+ //\r
+ ZeroMem (&CmdTrbStopED, sizeof (CmdTrbStopED));\r
+ CmdTrbStopED.CycleBit = 1;\r
+ CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;\r
+ CmdTrbStopED.EDID = Dci;\r
+ CmdTrbStopED.SlotId = SlotId;\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbStopED,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));\r
+ }\r
+\r
+ Xhc->PendingUrb = NULL;\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Reset endpoint through XHCI's Reset_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param Dci The device context index of endpoint.\r
+\r
+ @retval EFI_SUCCESS Reset endpoint successfully.\r
+ @retval Others Failed to reset endpoint.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcResetEndpoint (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ CMD_TRB_RESET_ENDPOINT CmdTrbResetED;\r
+\r
+ DEBUG ((DEBUG_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));\r
+\r
+ //\r
+ // Send stop endpoint command to transit Endpoint from running to stop state\r
+ //\r
+ ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));\r
+ CmdTrbResetED.CycleBit = 1;\r
+ CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;\r
+ CmdTrbResetED.EDID = Dci;\r
+ CmdTrbResetED.SlotId = SlotId;\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbResetED,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param Dci The device context index of endpoint.\r
+ @param Urb The dequeue pointer of the transfer ring specified\r
+ by the urb to be updated.\r
+\r
+ @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r
+ @retval Others Failed to set transfer ring dequeue pointer.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetTrDequeuePointer (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 Dci,\r
+ IN URB *Urb\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+ CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+\r
+ DEBUG ((DEBUG_VERBOSE, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));\r
+\r
+ //\r
+ // Send stop endpoint command to transit Endpoint from running to stop state\r
+ //\r
+ ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));\r
+ CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;\r
+ CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
+ CmdSetTRDeq.CycleBit = 1;\r
+ CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;\r
+ CmdSetTRDeq.Endpoint = Dci;\r
+ CmdSetTRDeq.SlotId = SlotId;\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdSetTRDeq,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Set interface through XHCI's Configure_Endpoint cmd.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param SlotId The slot id to be configured.\r
+ @param DeviceSpeed The device's speed.\r
+ @param ConfigDesc The pointer to the usb device configuration descriptor.\r
+ @param Request USB device request to send.\r
+\r
+ @retval EFI_SUCCESS Successfully set interface.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetInterface (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
+ IN EFI_USB_DEVICE_REQUEST *Request\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;\r
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;\r
+ USB_INTERFACE_DESCRIPTOR *IfDesc;\r
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
+ UINTN NumEp;\r
+ UINTN EpIndex;\r
+ UINT8 EpAddr;\r
+ UINT8 Direction;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ VOID *RingSeg;\r
+\r
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ INPUT_CONTEXT *InputContext;\r
+ DEVICE_CONTEXT *OutputContext;\r
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
+ //\r
+ // XHCI 4.6.6 Configure Endpoint\r
+ // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r
+ // Context and Add Context flags as follows:\r
+ // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop\r
+ // Context and Add Context flags to '0'.\r
+ //\r
+ // Except the interface indicated by Reqeust->Index, no impact to other interfaces.\r
+ // So the default Drop Context and Add Context flags can be '0' to cover 1).\r
+ //\r
+ ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
+ CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r
+\r
+ ASSERT (ConfigDesc != NULL);\r
\r
MaxDci = 0;\r
\r
+ IfDescActive = NULL;\r
+ IfDescSet = NULL;\r
+\r
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
- for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
- while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {\r
+ if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {\r
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {\r
+ if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {\r
+ //\r
+ // Find out the active interface descriptor.\r
+ //\r
+ IfDescActive = IfDesc;\r
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {\r
+ //\r
+ // Find out the interface descriptor to set.\r
+ //\r
+ IfDescSet = IfDesc;\r
+ }\r
+ }\r
}\r
\r
- NumEp = IfDesc->NumEndpoints;\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ }\r
+\r
+ //\r
+ // XHCI 4.6.6 Configure Endpoint\r
+ // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r
+ // Context and Add Context flags as follows:\r
+ // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set\r
+ // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.\r
+ // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set\r
+ // the Drop Context flag to '1' and Add Context flag to '0'.\r
+ // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context\r
+ // and Add Context flags shall be set to '1'.\r
+ //\r
+ // Below codes are to cover 2), 3) and 4).\r
+ //\r
\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
+ if ((IfDescActive != NULL) && (IfDescSet != NULL)) {\r
+ NumEp = IfDescActive->NumEndpoints;\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);\r
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
\r
+ if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ }\r
+\r
EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
\r
MaxDci = Dci;\r
}\r
\r
- InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
- InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r
-\r
- if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
- //\r
- // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
- //\r
- InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
- } else {\r
- InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.\r
+ //\r
+ Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
}\r
\r
- switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
- case USB_ENDPOINT_BULK:\r
- if (Direction == EfiUsbDataIn) {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
- } else {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
- }\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.\r
+ //\r
+ if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {\r
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;\r
+ if (RingSeg != NULL) {\r
+ UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
+ }\r
\r
- InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
- if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
- }\r
-\r
- break;\r
- case USB_ENDPOINT_ISO:\r
- if (Direction == EfiUsbDataIn) {\r
- InputContext->EP[Dci-1].CErr = 0;\r
- InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
- } else {\r
- InputContext->EP[Dci-1].CErr = 0;\r
- InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
- }\r
- break;\r
- case USB_ENDPOINT_INTERRUPT:\r
- if (Direction == EfiUsbDataIn) {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
- } else {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
- }\r
- InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
- InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
- //\r
- // Get the bInterval from descriptor and init the the interval field of endpoint context\r
- //\r
- if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
- Interval = EpDesc->Interval;\r
- //\r
- // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.\r
- //\r
- InputContext->EP[Dci-1].Interval = 6;\r
- } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
- Interval = EpDesc->Interval;\r
- ASSERT (Interval >= 1 && Interval <= 16);\r
- //\r
- // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
- //\r
- InputContext->EP[Dci-1].Interval = Interval - 1;\r
- InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
- InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r
- InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
- InputContext->EP[Dci-1].CErr = 3;\r
- }\r
-\r
- if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
- }\r
- break;\r
-\r
- case USB_ENDPOINT_CONTROL:\r
- default:\r
- ASSERT (0);\r
- break;\r
+ FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;\r
}\r
\r
- PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
- PhyAddr &= ~(0x0F);\r
- PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
- InputContext->EP[Dci-1].PtrLo = PhyAddr;\r
- InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
+ //\r
+ // Set the Drop Context flag to '1'.\r
+ //\r
+ InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);\r
\r
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
- }\r
\r
- InputContext->InputControlContext.Dword2 |= BIT0;\r
- InputContext->Slot.ContextEntries = MaxDci;\r
- //\r
- // configure endpoint\r
- //\r
- ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
- CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
- CmdTrbCfgEP.CycleBit = 1;\r
- CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
- CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT_EFI_ERROR(Status);\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate\r
+ // Interface setting, to '0'.\r
+ //\r
+ // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.\r
+ //\r
+\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 4) For each endpoint enabled by the Configure Endpoint Command:\r
+ // a. Allocate a Transfer Ring.\r
+ // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.\r
+ // c. Initialize the Endpoint Context data structure.\r
+ //\r
+ Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);\r
+ if (Dci > MaxDci) {\r
+ MaxDci = Dci;\r
+ }\r
+\r
+ InputContext->InputControlContext.Dword2 |= BIT0;\r
+ InputContext->Slot.ContextEntries = MaxDci;\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 5) Issue and successfully complete a Configure Endpoint Command.\r
+ //\r
+ ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
+ CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.CycleBit = 1;\r
+ CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
+ CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
+ DEBUG ((DEBUG_INFO, "SetInterface: Configure Endpoint\n"));\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));\r
+ } else {\r
+ //\r
+ // Update the active AlternateSetting.\r
+ //\r
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;\r
+ }\r
+ }\r
\r
return Status;\r
}\r
\r
/**\r
- Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
+ Set interface through XHCI's Configure_Endpoint cmd.\r
\r
@param Xhc The XHCI Instance.\r
@param SlotId The slot id to be configured.\r
@param DeviceSpeed The device's speed.\r
@param ConfigDesc The pointer to the usb device configuration descriptor.\r
+ @param Request USB device request to send.\r
\r
- @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
+ @retval EFI_SUCCESS Successfully set interface.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-XhcSetConfigCmd64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 DeviceSpeed,\r
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
+XhcSetInterface64 (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 DeviceSpeed,\r
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
+ IN EFI_USB_DEVICE_REQUEST *Request\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;\r
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;\r
+ USB_INTERFACE_DESCRIPTOR *IfDesc;\r
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
+ UINTN NumEp;\r
+ UINTN EpIndex;\r
+ UINT8 EpAddr;\r
+ UINT8 Direction;\r
+ UINT8 Dci;\r
+ UINT8 MaxDci;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
+ VOID *RingSeg;\r
\r
- USB_INTERFACE_DESCRIPTOR *IfDesc;\r
- USB_ENDPOINT_DESCRIPTOR *EpDesc;\r
- UINT8 Index;\r
- UINTN NumEp;\r
- UINTN EpIndex;\r
- UINT8 EpAddr;\r
- UINT8 Direction;\r
- UINT8 Dci;\r
- UINT8 MaxDci;\r
- UINT32 PhyAddr;\r
- UINT8 Interval;\r
-\r
- TRANSFER_RING *EndpointTransferRing;\r
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
INPUT_CONTEXT_64 *InputContext;\r
DEVICE_CONTEXT_64 *OutputContext;\r
EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
- //\r
- // 4.6.6 Configure Endpoint\r
- //\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
+ //\r
+ // XHCI 4.6.6 Configure Endpoint\r
+ // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r
+ // Context and Add Context flags as follows:\r
+ // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop\r
+ // Context and Add Context flags to '0'.\r
+ //\r
+ // Except the interface indicated by Reqeust->Index, no impact to other interfaces.\r
+ // So the default Drop Context and Add Context flags can be '0' to cover 1).\r
+ //\r
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));\r
\r
\r
MaxDci = 0;\r
\r
+ IfDescActive = NULL;\r
+ IfDescSet = NULL;\r
+\r
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r
- for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r
- while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {\r
+ if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {\r
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {\r
+ if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {\r
+ //\r
+ // Find out the active interface descriptor.\r
+ //\r
+ IfDescActive = IfDesc;\r
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {\r
+ //\r
+ // Find out the interface descriptor to set.\r
+ //\r
+ IfDescSet = IfDesc;\r
+ }\r
+ }\r
}\r
\r
- NumEp = IfDesc->NumEndpoints;\r
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
+ }\r
+\r
+ //\r
+ // XHCI 4.6.6 Configure Endpoint\r
+ // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r
+ // Context and Add Context flags as follows:\r
+ // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set\r
+ // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.\r
+ // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set\r
+ // the Drop Context flag to '1' and Add Context flag to '0'.\r
+ // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context\r
+ // and Add Context flags shall be set to '1'.\r
+ //\r
+ // Below codes are to cover 2), 3) and 4).\r
+ //\r
\r
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r
+ if ((IfDescActive != NULL) && (IfDescSet != NULL)) {\r
+ NumEp = IfDescActive->NumEndpoints;\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);\r
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
\r
+ if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+ continue;\r
+ }\r
+\r
EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r
Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r
\r
MaxDci = Dci;\r
}\r
\r
- InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r
- InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r
-\r
- if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r
- //\r
- // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r
- //\r
- InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
- } else {\r
- InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.\r
+ //\r
+ Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
}\r
\r
- switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r
- case USB_ENDPOINT_BULK:\r
- if (Direction == EfiUsbDataIn) {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r
- } else {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r
- }\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.\r
+ //\r
+ if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {\r
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;\r
+ if (RingSeg != NULL) {\r
+ UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r
+ }\r
\r
- InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
- if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
- }\r
-\r
- break;\r
- case USB_ENDPOINT_ISO:\r
- if (Direction == EfiUsbDataIn) {\r
- InputContext->EP[Dci-1].CErr = 0;\r
- InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r
- } else {\r
- InputContext->EP[Dci-1].CErr = 0;\r
- InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
- }\r
- break;\r
- case USB_ENDPOINT_INTERRUPT:\r
- if (Direction == EfiUsbDataIn) {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r
- } else {\r
- InputContext->EP[Dci-1].CErr = 3;\r
- InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r
- }\r
- InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
- InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r
- //\r
- // Get the bInterval from descriptor and init the the interval field of endpoint context\r
- //\r
- if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r
- Interval = EpDesc->Interval;\r
- //\r
- // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.\r
- //\r
- InputContext->EP[Dci-1].Interval = 6;\r
- } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r
- Interval = EpDesc->Interval;\r
- ASSERT (Interval >= 1 && Interval <= 16);\r
- //\r
- // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r
- //\r
- InputContext->EP[Dci-1].Interval = Interval - 1;\r
- InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r
- InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r
- InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r
- InputContext->EP[Dci-1].CErr = 3;\r
- }\r
-\r
- if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r
- }\r
- break;\r
-\r
- case USB_ENDPOINT_CONTROL:\r
- default:\r
- ASSERT (0);\r
- break;\r
+ FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);\r
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;\r
}\r
\r
- PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
- PhyAddr &= ~(0x0F);\r
- PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
- InputContext->EP[Dci-1].PtrLo = PhyAddr;\r
- InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r
+ //\r
+ // Set the Drop Context flag to '1'.\r
+ //\r
+ InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);\r
\r
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
}\r
- IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
- }\r
\r
- InputContext->InputControlContext.Dword2 |= BIT0;\r
- InputContext->Slot.ContextEntries = MaxDci;\r
- //\r
- // configure endpoint\r
- //\r
- ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
- CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
- CmdTrbCfgEP.CycleBit = 1;\r
- CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
- CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r
- Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT_EFI_ERROR(Status);\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate\r
+ // Interface setting, to '0'.\r
+ //\r
+ // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.\r
+ //\r
+\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 4) For each endpoint enabled by the Configure Endpoint Command:\r
+ // a. Allocate a Transfer Ring.\r
+ // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.\r
+ // c. Initialize the Endpoint Context data structure.\r
+ //\r
+ Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);\r
+ if (Dci > MaxDci) {\r
+ MaxDci = Dci;\r
+ }\r
+\r
+ InputContext->InputControlContext.Dword2 |= BIT0;\r
+ InputContext->Slot.ContextEntries = MaxDci;\r
+ //\r
+ // XHCI 4.3.6 - Setting Alternate Interfaces\r
+ // 5) Issue and successfully complete a Configure Endpoint Command.\r
+ //\r
+ ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
+ CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.CycleBit = 1;\r
+ CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
+ CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
+ DEBUG ((DEBUG_INFO, "SetInterface64: Configure Endpoint\n"));\r
+ Status = XhcCmdTransfer (\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));\r
+ } else {\r
+ //\r
+ // Update the active AlternateSetting.\r
+ //\r
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;\r
+ }\r
+ }\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcEvaluateContext (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT32 MaxPacketSize\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT32 MaxPacketSize\r
)\r
{\r
EFI_STATUS Status;\r
CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
INPUT_CONTEXT *InputContext;\r
+ DEVICE_CONTEXT *OutputContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
\r
//\r
// 4.6.7 Evaluate Context\r
//\r
- InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
+ InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r
\r
+ CopyMem (&InputContext->EP[0], &OutputContext->EP[0], sizeof (ENDPOINT_CONTEXT));\r
+\r
InputContext->InputControlContext.Dword2 |= BIT1;\r
InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r
+ InputContext->EP[0].EPState = 0;\r
\r
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
- CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);\r
- CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
+ CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbEvalu.CycleBit = 1;\r
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r
+ DEBUG ((DEBUG_INFO, "Evaluate context\n"));\r
Status = XhcCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
- ASSERT (!EFI_ERROR(Status));\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));\r
+ }\r
\r
return Status;\r
}\r
EFI_STATUS\r
EFIAPI\r
XhcEvaluateContext64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT32 MaxPacketSize\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT32 MaxPacketSize\r
)\r
{\r
EFI_STATUS Status;\r
CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r
EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
INPUT_CONTEXT_64 *InputContext;\r
+ DEVICE_CONTEXT_64 *OutputContext;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
\r
//\r
// 4.6.7 Evaluate Context\r
//\r
- InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
+ InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r
\r
+ CopyMem (&InputContext->EP[0], &OutputContext->EP[0], sizeof (ENDPOINT_CONTEXT_64));\r
+\r
InputContext->InputControlContext.Dword2 |= BIT1;\r
InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r
+ InputContext->EP[0].EPState = 0;\r
\r
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r
- CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);\r
- CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
+ CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbEvalu.CycleBit = 1;\r
CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r
CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r
+ DEBUG ((DEBUG_INFO, "Evaluate context\n"));\r
Status = XhcCmdTransfer (\r
Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,\r
XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
);\r
- ASSERT (!EFI_ERROR(Status));\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));\r
+ }\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
\r
**/\r
EFI_STATUS\r
XhcConfigHubContext (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 PortNum,\r
- IN UINT8 TTT,\r
- IN UINT8 MTT\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 PortNum,\r
+ IN UINT8 TTT,\r
+ IN UINT8 MTT\r
)\r
{\r
EFI_STATUS Status;\r
-\r
EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
INPUT_CONTEXT *InputContext;\r
DEVICE_CONTEXT *OutputContext;\r
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
//\r
// Copy the slot context from OutputContext to Input context\r
//\r
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r
InputContext->Slot.Hub = 1;\r
InputContext->Slot.PortNum = PortNum;\r
InputContext->Slot.TTT = TTT;\r
InputContext->Slot.MTT = MTT;\r
\r
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
- CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r
+ CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbCfgEP.CycleBit = 1;\r
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r
+ DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));\r
Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT (!EFI_ERROR(Status));\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));\r
+ }\r
\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
XhcConfigHubContext64 (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 SlotId,\r
- IN UINT8 PortNum,\r
- IN UINT8 TTT,\r
- IN UINT8 MTT\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 SlotId,\r
+ IN UINT8 PortNum,\r
+ IN UINT8 TTT,\r
+ IN UINT8 MTT\r
)\r
{\r
EFI_STATUS Status;\r
-\r
EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r
INPUT_CONTEXT_64 *InputContext;\r
DEVICE_CONTEXT_64 *OutputContext;\r
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r
+ EFI_PHYSICAL_ADDRESS PhyAddr;\r
\r
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r
InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r
//\r
// Copy the slot context from OutputContext to Input context\r
//\r
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r
InputContext->Slot.Hub = 1;\r
InputContext->Slot.PortNum = PortNum;\r
InputContext->Slot.TTT = TTT;\r
InputContext->Slot.MTT = MTT;\r
\r
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r
- CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r
- CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r
+ CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r
+ CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
CmdTrbCfgEP.CycleBit = 1;\r
CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r
CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r
- DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r
+ DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));\r
Status = XhcCmdTransfer (\r
- Xhc,\r
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r
- XHC_GENERIC_TIMEOUT,\r
- (TRB_TEMPLATE **) (UINTN) &EvtTrb\r
- );\r
- ASSERT (!EFI_ERROR(Status));\r
+ Xhc,\r
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,\r
+ XHC_GENERIC_TIMEOUT,\r
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));\r
+ }\r
\r
return Status;\r
}\r
-\r
-\r
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