MdeModulePkg: Clean up source files

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 21fdcf130a5000e4e7df41ec59d9a629d53b9237..6a2ef4cd5d48270aee5f19364b5597aa5795a576 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -2,7 +2,7 @@
 \r
   XHCI transfer scheduling routines.\r
 \r
-Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -201,7 +201,7 @@ XhcFreeUrb (
   if ((Xhc == NULL) || (Urb == NULL)) {\r
     return;\r
   }\r
-  \r
+\r
   if (Urb->DataMap != NULL) {\r
     Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);\r
   }\r
@@ -269,15 +269,15 @@ XhcCreateTransferTrb (
     } else {\r
       MapOp = EfiPciIoOperationBusMasterRead;\r
     }\r
-    \r
+\r
     Len = Urb->DataLen;\r
     Status  = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r
-    \r
+\r
     if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r
       DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));\r
       return EFI_OUT_OF_RESOURCES;\r
     }\r
-    \r
+\r
     Urb->DataPhy  = (VOID *) ((UINTN) PhyAddr);\r
     Urb->DataMap  = Map;\r
   }\r
@@ -469,7 +469,7 @@ XhcInitSched (
   VOID                  *Dcbaa;\r
   EFI_PHYSICAL_ADDRESS  DcbaaPhy;\r
   UINT64                CmdRing;\r
-  EFI_PHYSICAL_ADDRESS  CmdRingPhy; \r
+  EFI_PHYSICAL_ADDRESS  CmdRingPhy;\r
   UINTN                 Entries;\r
   UINT32                MaxScratchpadBufs;\r
   UINT64                *ScratchBuf;\r
@@ -520,7 +520,7 @@ XhcInitSched (
     ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);\r
     ASSERT (ScratchEntryMap != NULL);\r
     Xhc->ScratchEntryMap = ScratchEntryMap;\r
-    \r
+\r
     //\r
     // Allocate the buffer to record the host address for each entry\r
     //\r
@@ -533,7 +533,7 @@ XhcInitSched (
                Xhc->PciIo,\r
                EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),\r
                Xhc->PageSize,\r
-               (VOID **) &ScratchBuf, \r
+               (VOID **) &ScratchBuf,\r
                &ScratchPhy,\r
                &Xhc->ScratchMap\r
                );\r
@@ -659,7 +659,7 @@ XhcRecoverHaltedEndpoint (
   }\r
   Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
   ASSERT (Dci < 32);\r
-  \r
+\r
   DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));\r
 \r
   //\r
@@ -721,7 +721,7 @@ XhcDequeueTrbFromEndpoint (
   }\r
   Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r
   ASSERT (Dci < 32);\r
-  \r
+\r
   DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));\r
 \r
   //\r
@@ -792,9 +792,9 @@ CreateEventRing (
   EventRing->TrbNumber        = EVENT_RING_TRB_NUMBER;\r
   EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
   EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r
-  \r
+\r
   DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);\r
-  \r
+\r
   //\r
   // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r
   // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.\r
@@ -953,7 +953,7 @@ XhcFreeSched (
 {\r
   UINT32                  Index;\r
   UINT64                  *ScratchEntry;\r
-  \r
+\r
   if (Xhc->ScratchBuf != NULL) {\r
     ScratchEntry = Xhc->ScratchEntry;\r
     for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {\r
@@ -974,14 +974,14 @@ XhcFreeSched (
     UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);\r
     Xhc->CmdRing.RingSeg0 = NULL;\r
   }\r
-  \r
+\r
   XhcFreeEventRing (Xhc,&Xhc->EventRing);\r
 \r
   if (Xhc->DCBAA != NULL) {\r
     UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));\r
     Xhc->DCBAA = NULL;\r
   }\r
-  \r
+\r
   //\r
   // Free memory pool at last\r
   //\r
@@ -1132,7 +1132,7 @@ XhcCheckUrbResult (
     if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {\r
       continue;\r
     }\r
-    \r
+\r
     //\r
     // Need convert pci device address to host address\r
     //\r
@@ -1149,12 +1149,12 @@ XhcCheckUrbResult (
       CheckedUrb = Xhc->PendingUrb;\r
     } else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {\r
       CheckedUrb = Urb;\r
-    } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {    \r
+    } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {\r
       CheckedUrb = AsyncUrb;\r
     } else {\r
       continue;\r
     }\r
-  \r
+\r
     switch (EvtTrb->Completecode) {\r
       case TRB_COMPLETION_STALL_ERROR:\r
         CheckedUrb->Result  |= EFI_USB_ERR_STALL;\r
@@ -1676,7 +1676,7 @@ XhcPollPortStatusChange (
         Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r
       }\r
     }\r
-  } \r
+  }\r
 \r
   return Status;\r
 }\r
@@ -3144,7 +3144,7 @@ XhcSetConfigCmd64 (
     if (Dci > MaxDci) {\r
       MaxDci = Dci;\r
     }\r
- \r
+\r
     IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r
   }\r
 \r