MdeModulePkg: fix completed xfer length in XhciDxe and XhciPei drivers

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index e29e727e3c20be0acac08b01dcae8262abd9930c..8ff194ea9b2b7846f49070f4e366bbc5a472a613 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -2,7 +2,7 @@
 \r
   XHCI transfer scheduling routines.\r
 \r
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -295,7 +295,7 @@ XhcCreateTransferTrb (
       TrbStart->TrbCtrSetup.wValue        = Urb->Request->Value;\r
       TrbStart->TrbCtrSetup.wIndex        = Urb->Request->Index;\r
       TrbStart->TrbCtrSetup.wLength       = Urb->Request->Length;\r
-      TrbStart->TrbCtrSetup.Lenth         = 8;\r
+      TrbStart->TrbCtrSetup.Length        = 8;\r
       TrbStart->TrbCtrSetup.IntTarget     = 0;\r
       TrbStart->TrbCtrSetup.IOC           = 1;\r
       TrbStart->TrbCtrSetup.IDT           = 1;\r
@@ -321,7 +321,7 @@ XhcCreateTransferTrb (
         TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
         TrbStart->TrbCtrData.TRBPtrLo  = XHC_LOW_32BIT(Urb->DataPhy);\r
         TrbStart->TrbCtrData.TRBPtrHi  = XHC_HIGH_32BIT(Urb->DataPhy);\r
-        TrbStart->TrbCtrData.Lenth     = (UINT32) Urb->DataLen;\r
+        TrbStart->TrbCtrData.Length    = (UINT32) Urb->DataLen;\r
         TrbStart->TrbCtrData.TDSize    = 0;\r
         TrbStart->TrbCtrData.IntTarget = 0;\r
         TrbStart->TrbCtrData.ISP       = 1;\r
@@ -387,7 +387,7 @@ XhcCreateTransferTrb (
         TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
         TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
         TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
-        TrbStart->TrbNormal.Lenth     = (UINT32) Len;\r
+        TrbStart->TrbNormal.Length    = (UINT32) Len;\r
         TrbStart->TrbNormal.TDSize    = 0;\r
         TrbStart->TrbNormal.IntTarget = 0;\r
         TrbStart->TrbNormal.ISP       = 1;\r
@@ -422,7 +422,7 @@ XhcCreateTransferTrb (
         TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
         TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
         TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
-        TrbStart->TrbNormal.Lenth     = (UINT32) Len;\r
+        TrbStart->TrbNormal.Length    = (UINT32) Len;\r
         TrbStart->TrbNormal.TDSize    = 0;\r
         TrbStart->TrbNormal.IntTarget = 0;\r
         TrbStart->TrbNormal.ISP       = 1;\r
@@ -1137,7 +1137,7 @@ XhcCheckUrbResult (
         if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r
             (TRBType == TRB_TYPE_NORMAL) ||\r
             (TRBType == TRB_TYPE_ISOCH)) {\r
-          CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Lenth);\r
+          CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);\r
         }\r
 \r
         break;\r
@@ -2606,7 +2606,12 @@ XhcInitializeEndpointContext (
           InputContext->EP[Dci-1].CErr   = 0;\r
           InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
         }\r
-        break;\r
+        //\r
+        // Do not support isochronous transfer now.\r
+        //\r
+        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
+        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+        continue;\r
       case USB_ENDPOINT_INTERRUPT:\r
         if (Direction == EfiUsbDataIn) {\r
           InputContext->EP[Dci-1].CErr   = 3;\r
@@ -2648,9 +2653,14 @@ XhcInitializeEndpointContext (
         break;\r
 \r
       case USB_ENDPOINT_CONTROL:\r
+        //\r
+        // Do not support control transfer now.\r
+        //\r
+        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
       default:\r
-        ASSERT (0);\r
-        break;\r
+        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));\r
+        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+        continue;\r
     }\r
 \r
     PhyAddr = UsbHcGetPciAddrForHostAddr (\r
@@ -2759,7 +2769,12 @@ XhcInitializeEndpointContext64 (
           InputContext->EP[Dci-1].CErr   = 0;\r
           InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
         }\r
-        break;\r
+        //\r
+        // Do not support isochronous transfer now.\r
+        //\r
+        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
+        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+        continue;\r
       case USB_ENDPOINT_INTERRUPT:\r
         if (Direction == EfiUsbDataIn) {\r
           InputContext->EP[Dci-1].CErr   = 3;\r
@@ -2801,9 +2816,14 @@ XhcInitializeEndpointContext64 (
         break;\r
 \r
       case USB_ENDPOINT_CONTROL:\r
+        //\r
+        // Do not support control transfer now.\r
+        //\r
+        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
       default:\r
-        ASSERT (0);\r
-        break;\r
+        DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));\r
+        EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+        continue;\r
     }\r
 \r
     PhyAddr = UsbHcGetPciAddrForHostAddr (\r