\r
This file contains the definition for XHCI host controller schedule routines.\r
\r
-Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINT32 RsvdZ9;\r
UINT32 RsvdZ10;\r
UINT32 RsvdZ11;\r
- \r
+\r
UINT32 RsvdZ12;\r
UINT32 RsvdZ13;\r
UINT32 RsvdZ14;\r
UINT32 RsvdZ5;\r
UINT32 RsvdZ6;\r
UINT32 RsvdZ7;\r
- \r
+\r
UINT32 RsvdZ8;\r
UINT32 RsvdZ9;\r
UINT32 RsvdZ10;\r
UINT32 RsvdZ11;\r
- \r
+\r
UINT32 RsvdZ12;\r
UINT32 RsvdZ13;\r
UINT32 RsvdZ14;\r