MdeModulePkg: Fix typo.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciSched.c

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
index 3ae151122240001d5b7170e788ae1d8c686dfee8..8e768bc470d597214d436d5e8e2d95c16904bcdf 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
@@ -1706,7 +1706,12 @@ XhcPeiSetConfigCmd (
             InputContext->EP[Dci-1].CErr   = 0;\r
             InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
           }\r
-          break;\r
+          //\r
+          // Do not support isochronous transfer now.\r
+          //\r
+          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
+          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+          continue;\r
         case USB_ENDPOINT_INTERRUPT:\r
           if (Direction == EfiUsbDataIn) {\r
             InputContext->EP[Dci-1].CErr   = 3;\r
@@ -1744,9 +1749,14 @@ XhcPeiSetConfigCmd (
           break;\r
 \r
         case USB_ENDPOINT_CONTROL:\r
+          //\r
+          // Do not support control transfer now.\r
+          //\r
+          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
         default:\r
-          ASSERT (FALSE);\r
-          break;\r
+          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unknown EP found, Transfer ring is not allocated.\n"));\r
+          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+          continue;\r
       }\r
 \r
       PhyAddr = UsbHcGetPciAddrForHostAddr (\r
@@ -1754,8 +1764,8 @@ XhcPeiSetConfigCmd (
                   ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r
                   sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
                   );\r
-      PhyAddr &= ~(0x0F);\r
-      PhyAddr |= ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
+      PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
+      PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
       InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
       InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
 \r
@@ -1899,7 +1909,12 @@ XhcPeiSetConfigCmd64 (
             InputContext->EP[Dci-1].CErr   = 0;\r
             InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r
           }\r
-          break;\r
+          //\r
+          // Do not support isochronous transfer now.\r
+          //\r
+          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r
+          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+          continue;\r
         case USB_ENDPOINT_INTERRUPT:\r
           if (Direction == EfiUsbDataIn) {\r
             InputContext->EP[Dci-1].CErr   = 3;\r
@@ -1937,9 +1952,14 @@ XhcPeiSetConfigCmd64 (
           break;\r
 \r
         case USB_ENDPOINT_CONTROL:\r
+          //\r
+          // Do not support control transfer now.\r
+          //\r
+          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r
         default:\r
-          ASSERT (0);\r
-          break;\r
+          DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unknown EP found, Transfer ring is not allocated.\n"));\r
+          EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r
+          continue;\r
       }\r
 \r
       PhyAddr = UsbHcGetPciAddrForHostAddr (\r
@@ -1948,8 +1968,8 @@ XhcPeiSetConfigCmd64 (
                   sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r
                   );\r
 \r
-      PhyAddr &= ~(0x0F);\r
-      PhyAddr |= ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
+      PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r
+      PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r
 \r
       InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r
       InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r
@@ -2618,6 +2638,7 @@ XhcPeiInitSched (
     ASSERT (ScratchEntry != NULL);\r
     Xhc->ScratchEntry = ScratchEntry;\r
 \r
+    ScratchPhy = 0;\r
     Status = UsbHcAllocateAlignedPages (\r
                EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),\r
                Xhc->PageSize,\r
@@ -2633,6 +2654,7 @@ XhcPeiInitSched (
     // Allocate each scratch buffer\r
     //\r
     for (Index = 0; Index < MaxScratchpadBufs; Index++) {\r
+      ScratchEntryPhy = 0;\r
       Status = UsbHcAllocateAlignedPages (\r
                  EFI_SIZE_TO_PAGES (Xhc->PageSize),\r
                  Xhc->PageSize,\r