EFI_STATUS\r
EFIAPI\r
EmmcPeimHcRwMmio (\r
- IN UINTN Address,\r
- IN BOOLEAN Read,\r
- IN UINT8 Count,\r
- IN OUT VOID *Data\r
+ IN UINTN Address,\r
+ IN BOOLEAN Read,\r
+ IN UINT8 Count,\r
+ IN OUT VOID *Data\r
)\r
{\r
- if ((Address == 0) || (Data == NULL)) {\r
+ if ((Address == 0) || (Data == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
switch (Count) {\r
case 1:\r
if (Read) {\r
- *(UINT8*)Data = MmioRead8 (Address);\r
+ *(UINT8 *)Data = MmioRead8 (Address);\r
} else {\r
- MmioWrite8 (Address, *(UINT8*)Data);\r
+ MmioWrite8 (Address, *(UINT8 *)Data);\r
}\r
+\r
break;\r
case 2:\r
if (Read) {\r
- *(UINT16*)Data = MmioRead16 (Address);\r
+ *(UINT16 *)Data = MmioRead16 (Address);\r
} else {\r
- MmioWrite16 (Address, *(UINT16*)Data);\r
+ MmioWrite16 (Address, *(UINT16 *)Data);\r
}\r
+\r
break;\r
case 4:\r
if (Read) {\r
- *(UINT32*)Data = MmioRead32 (Address);\r
+ *(UINT32 *)Data = MmioRead32 (Address);\r
} else {\r
- MmioWrite32 (Address, *(UINT32*)Data);\r
+ MmioWrite32 (Address, *(UINT32 *)Data);\r
}\r
+\r
break;\r
case 8:\r
if (Read) {\r
- *(UINT64*)Data = MmioRead64 (Address);\r
+ *(UINT64 *)Data = MmioRead64 (Address);\r
} else {\r
- MmioWrite64 (Address, *(UINT64*)Data);\r
+ MmioWrite64 (Address, *(UINT64 *)Data);\r
}\r
+\r
break;\r
default:\r
ASSERT (FALSE);\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcOrMmio (\r
- IN UINTN Address,\r
- IN UINT8 Count,\r
- IN VOID *OrData\r
+ IN UINTN Address,\r
+ IN UINT8 Count,\r
+ IN VOID *OrData\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Data;\r
- UINT64 Or;\r
+ EFI_STATUS Status;\r
+ UINT64 Data;\r
+ UINT64 Or;\r
\r
Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);\r
if (EFI_ERROR (Status)) {\r
}\r
\r
if (Count == 1) {\r
- Or = *(UINT8*) OrData;\r
+ Or = *(UINT8 *)OrData;\r
} else if (Count == 2) {\r
- Or = *(UINT16*) OrData;\r
+ Or = *(UINT16 *)OrData;\r
} else if (Count == 4) {\r
- Or = *(UINT32*) OrData;\r
+ Or = *(UINT32 *)OrData;\r
} else if (Count == 8) {\r
- Or = *(UINT64*) OrData;\r
+ Or = *(UINT64 *)OrData;\r
} else {\r
return EFI_INVALID_PARAMETER;\r
}\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcAndMmio (\r
- IN UINTN Address,\r
- IN UINT8 Count,\r
- IN VOID *AndData\r
+ IN UINTN Address,\r
+ IN UINT8 Count,\r
+ IN VOID *AndData\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Data;\r
- UINT64 And;\r
+ EFI_STATUS Status;\r
+ UINT64 Data;\r
+ UINT64 And;\r
\r
Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);\r
if (EFI_ERROR (Status)) {\r
}\r
\r
if (Count == 1) {\r
- And = *(UINT8*) AndData;\r
+ And = *(UINT8 *)AndData;\r
} else if (Count == 2) {\r
- And = *(UINT16*) AndData;\r
+ And = *(UINT16 *)AndData;\r
} else if (Count == 4) {\r
- And = *(UINT32*) AndData;\r
+ And = *(UINT32 *)AndData;\r
} else if (Count == 8) {\r
- And = *(UINT64*) AndData;\r
+ And = *(UINT64 *)AndData;\r
} else {\r
return EFI_INVALID_PARAMETER;\r
}\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcCheckMmioSet (\r
- IN UINTN Address,\r
- IN UINT8 Count,\r
- IN UINT64 MaskValue,\r
- IN UINT64 TestValue\r
+ IN UINTN Address,\r
+ IN UINT8 Count,\r
+ IN UINT64 MaskValue,\r
+ IN UINT64 TestValue\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Value;\r
+ EFI_STATUS Status;\r
+ UINT64 Value;\r
\r
//\r
// Access PCI MMIO space to see if the value is the tested one.\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimHcWaitMmioSet (\r
- IN UINTN Address,\r
- IN UINT8 Count,\r
- IN UINT64 MaskValue,\r
- IN UINT64 TestValue,\r
- IN UINT64 Timeout\r
+ IN UINTN Address,\r
+ IN UINT8 Count,\r
+ IN UINT64 MaskValue,\r
+ IN UINT64 TestValue,\r
+ IN UINT64 Timeout\r
)\r
{\r
- EFI_STATUS Status;\r
- BOOLEAN InfiniteWait;\r
+ EFI_STATUS Status;\r
+ BOOLEAN InfiniteWait;\r
\r
if (Timeout == 0) {\r
InfiniteWait = TRUE;\r
**/\r
EFI_STATUS\r
EmmcPeimHcReset (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 SwReset;\r
+ EFI_STATUS Status;\r
+ UINT8 SwReset;\r
\r
SwReset = 0xFF;\r
Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);\r
DEBUG ((DEBUG_INFO, "EmmcPeimHcReset: reset done with %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
// Enable all interrupt after reset all.\r
//\r
**/\r
EFI_STATUS\r
EmmcPeimHcEnableInterrupt (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT16 IntStatus;\r
+ EFI_STATUS Status;\r
+ UINT16 IntStatus;\r
\r
//\r
// Enable all bits in Error Interrupt Status Enable Register\r
//\r
IntStatus = 0xFFFF;\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Enable all bits in Normal Interrupt Status Enable Register\r
//\r
IntStatus = 0xFFFF;\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimHcGetCapability (\r
- IN UINTN Bar,\r
- OUT EMMC_HC_SLOT_CAP *Capability\r
+ IN UINTN Bar,\r
+ OUT EMMC_HC_SLOT_CAP *Capability\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Cap;\r
+ EFI_STATUS Status;\r
+ UINT64 Cap;\r
\r
Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r
if (EFI_ERROR (Status)) {\r
**/\r
EFI_STATUS\r
EmmcPeimHcCardDetect (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT16 Data;\r
- UINT32 PresentState;\r
+ EFI_STATUS Status;\r
+ UINT16 Data;\r
+ UINT32 PresentState;\r
\r
//\r
// Check Normal Interrupt Status Register\r
**/\r
EFI_STATUS\r
EmmcPeimHcStopClock (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 PresentState;\r
- UINT16 ClockCtrl;\r
+ EFI_STATUS Status;\r
+ UINT32 PresentState;\r
+ UINT16 ClockCtrl;\r
\r
//\r
// Ensure no SD transactions are occurring on the SD Bus by\r
//\r
// Set SD Clock Enable in the Clock Control register to 0\r
//\r
- ClockCtrl = (UINT16)~BIT2;\r
- Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
+ ClockCtrl = (UINT16) ~BIT2;\r
+ Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimHcClockSupply (\r
- IN UINTN Bar,\r
- IN UINT64 ClockFreq\r
+ IN UINTN Bar,\r
+ IN UINT64 ClockFreq\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_HC_SLOT_CAP Capability;\r
- UINT32 BaseClkFreq;\r
- UINT32 SettingFreq;\r
- UINT32 Divisor;\r
- UINT32 Remainder;\r
- UINT16 ControllerVer;\r
- UINT16 ClockCtrl;\r
+ EFI_STATUS Status;\r
+ EMMC_HC_SLOT_CAP Capability;\r
+ UINT32 BaseClkFreq;\r
+ UINT32 SettingFreq;\r
+ UINT32 Divisor;\r
+ UINT32 Remainder;\r
+ UINT16 ControllerVer;\r
+ UINT16 ClockCtrl;\r
\r
//\r
// Calculate a divisor for SD clock frequency\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
ASSERT (Capability.BaseClkFreq != 0);\r
\r
BaseClkFreq = Capability.BaseClkFreq;\r
if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r
break;\r
}\r
+\r
if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r
- SettingFreq ++;\r
+ SettingFreq++;\r
}\r
}\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
//\r
if (((Divisor - 1) & Divisor) != 0) {\r
Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r
}\r
+\r
ASSERT (Divisor <= 0x80);\r
ClockCtrl = (Divisor & 0xFF) << 8;\r
} else {\r
// Supply clock frequency with specified divisor\r
//\r
ClockCtrl |= BIT0;\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r
return Status;\r
// Set SD Clock Enable in the Clock Control register to 1\r
//\r
ClockCtrl = BIT2;\r
- Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
+ Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimHcPowerControl (\r
- IN UINTN Bar,\r
- IN UINT8 PowerCtrl\r
+ IN UINTN Bar,\r
+ IN UINT8 PowerCtrl\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
//\r
// Clr SD Bus Power\r
//\r
- PowerCtrl &= (UINT8)~BIT0;\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
+ PowerCtrl &= (UINT8) ~BIT0;\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
// Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
//\r
PowerCtrl |= BIT0;\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimHcSetBusWidth (\r
- IN UINTN Bar,\r
- IN UINT16 BusWidth\r
+ IN UINTN Bar,\r
+ IN UINT16 BusWidth\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HostCtrl1;\r
+ EFI_STATUS Status;\r
+ UINT8 HostCtrl1;\r
\r
if (BusWidth == 1) {\r
- HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r
- Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
+ HostCtrl1 = (UINT8) ~(BIT5 | BIT1);\r
+ Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
} else if (BusWidth == 4) {\r
Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
HostCtrl1 |= BIT1;\r
- HostCtrl1 &= (UINT8)~BIT5;\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
+ HostCtrl1 &= (UINT8) ~BIT5;\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
} else if (BusWidth == 8) {\r
Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- HostCtrl1 &= (UINT8)~BIT1;\r
+\r
+ HostCtrl1 &= (UINT8) ~BIT1;\r
HostCtrl1 |= BIT5;\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
} else {\r
ASSERT (FALSE);\r
return EFI_INVALID_PARAMETER;\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitClockFreq (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_HC_SLOT_CAP Capability;\r
- UINT32 InitFreq;\r
+ EFI_STATUS Status;\r
+ EMMC_HC_SLOT_CAP Capability;\r
+ UINT32 InitFreq;\r
\r
//\r
// Calculate a divisor for SD clock frequency\r
//\r
return EFI_UNSUPPORTED;\r
}\r
+\r
//\r
// Supply 400KHz clock frequency at initialization phase.\r
//\r
InitFreq = 400;\r
- Status = EmmcPeimHcClockSupply (Bar, InitFreq);\r
+ Status = EmmcPeimHcClockSupply (Bar, InitFreq);\r
return Status;\r
}\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitPowerVoltage (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_HC_SLOT_CAP Capability;\r
- UINT8 MaxVoltage;\r
- UINT8 HostCtrl2;\r
+ EFI_STATUS Status;\r
+ EMMC_HC_SLOT_CAP Capability;\r
+ UINT8 MaxVoltage;\r
+ UINT8 HostCtrl2;\r
\r
//\r
// Get the support voltage of the Host Controller\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Calculate supported maximum voltage according to SD Bus Voltage Select\r
//\r
//\r
MaxVoltage = 0x0A;\r
HostCtrl2 = BIT3;\r
- Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
MicroSecondDelay (5000);\r
} else {\r
ASSERT (FALSE);\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitTimeoutCtrl (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 Timeout;\r
+ EFI_STATUS Status;\r
+ UINT8 Timeout;\r
\r
Timeout = 0x0E;\r
Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitHost (\r
- IN UINTN Bar\r
+ IN UINTN Bar\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = EmmcPeimHcInitClockFreq (Bar);\r
if (EFI_ERROR (Status)) {\r
**/\r
EFI_STATUS\r
EmmcPeimHcLedOnOff (\r
- IN UINTN Bar,\r
- IN BOOLEAN On\r
+ IN UINTN Bar,\r
+ IN BOOLEAN On\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HostCtrl1;\r
+ EFI_STATUS Status;\r
+ UINT8 HostCtrl1;\r
\r
if (On) {\r
HostCtrl1 = BIT0;\r
Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
} else {\r
- HostCtrl1 = (UINT8)~BIT0;\r
+ HostCtrl1 = (UINT8) ~BIT0;\r
Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
}\r
\r
**/\r
EFI_STATUS\r
BuildAdmaDescTable (\r
- IN EMMC_TRB *Trb\r
+ IN EMMC_TRB *Trb\r
)\r
{\r
- EFI_PHYSICAL_ADDRESS Data;\r
- UINT64 DataLen;\r
- UINT64 Entries;\r
- UINT32 Index;\r
- UINT64 Remaining;\r
- UINT32 Address;\r
+ EFI_PHYSICAL_ADDRESS Data;\r
+ UINT64 DataLen;\r
+ UINT64 Entries;\r
+ UINT32 Index;\r
+ UINT64 Remaining;\r
+ UINT32 Address;\r
\r
Data = Trb->DataPhy;\r
DataLen = Trb->DataLen;\r
if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
//\r
// Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
// for 32-bit address descriptor table.\r
Address = (UINT32)Data;\r
for (Index = 0; Index < Entries; Index++) {\r
if (Remaining <= ADMA_MAX_DATA_PER_LINE) {\r
- Trb->AdmaDesc[Index].Valid = 1;\r
- Trb->AdmaDesc[Index].Act = 2;\r
+ Trb->AdmaDesc[Index].Valid = 1;\r
+ Trb->AdmaDesc[Index].Act = 2;\r
Trb->AdmaDesc[Index].Length = (UINT16)Remaining;\r
Trb->AdmaDesc[Index].Address = Address;\r
break;\r
} else {\r
- Trb->AdmaDesc[Index].Valid = 1;\r
- Trb->AdmaDesc[Index].Act = 2;\r
+ Trb->AdmaDesc[Index].Valid = 1;\r
+ Trb->AdmaDesc[Index].Act = 2;\r
Trb->AdmaDesc[Index].Length = 0;\r
Trb->AdmaDesc[Index].Address = Address;\r
}\r
**/\r
EMMC_TRB *\r
EmmcPeimCreateTrb (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN EMMC_COMMAND_PACKET *Packet\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN EMMC_COMMAND_PACKET *Packet\r
)\r
{\r
- EMMC_TRB *Trb;\r
- EFI_STATUS Status;\r
- EMMC_HC_SLOT_CAP Capability;\r
- EDKII_IOMMU_OPERATION MapOp;\r
- UINTN MapLength;\r
+ EMMC_TRB *Trb;\r
+ EFI_STATUS Status;\r
+ EMMC_HC_SLOT_CAP Capability;\r
+ EDKII_IOMMU_OPERATION MapOp;\r
+ UINTN MapLength;\r
\r
//\r
// Calculate a divisor for SD clock frequency\r
\r
if (Trb->DataLen != 0) {\r
MapLength = Trb->DataLen;\r
- Status = IoMmuMap (MapOp, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);\r
+ Status = IoMmuMap (MapOp, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);\r
\r
if (EFI_ERROR (Status) || (MapLength != Trb->DataLen)) {\r
DEBUG ((DEBUG_ERROR, "EmmcPeimCreateTrb: Fail to map data buffer.\n"));\r
Trb->Mode = EmmcNoData;\r
} else if (Capability.Adma2 != 0) {\r
Trb->Mode = EmmcAdmaMode;\r
- Status = BuildAdmaDescTable (Trb);\r
+ Status = BuildAdmaDescTable (Trb);\r
if (EFI_ERROR (Status)) {\r
goto Error;\r
}\r
Trb->Mode = EmmcPioMode;\r
}\r
}\r
+\r
return Trb;\r
\r
Error:\r
**/\r
VOID\r
EmmcPeimFreeTrb (\r
- IN EMMC_TRB *Trb\r
+ IN EMMC_TRB *Trb\r
)\r
{\r
if ((Trb != NULL) && (Trb->DataMap != NULL)) {\r
if (Trb != NULL) {\r
FreePool (Trb);\r
}\r
+\r
return;\r
}\r
\r
**/\r
EFI_STATUS\r
EmmcPeimCheckTrbEnv (\r
- IN UINTN Bar,\r
- IN EMMC_TRB *Trb\r
+ IN UINTN Bar,\r
+ IN EMMC_TRB *Trb\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_COMMAND_PACKET *Packet;\r
- UINT32 PresentState;\r
+ EFI_STATUS Status;\r
+ EMMC_COMMAND_PACKET *Packet;\r
+ UINT32 PresentState;\r
\r
Packet = Trb->Packet;\r
\r
if ((Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) ||\r
(Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR1b) ||\r
- (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR5b)) {\r
+ (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR5b))\r
+ {\r
//\r
// Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r
// the Present State register to be 0\r
**/\r
EFI_STATUS\r
EmmcPeimWaitTrbEnv (\r
- IN UINTN Bar,\r
- IN EMMC_TRB *Trb\r
+ IN UINTN Bar,\r
+ IN EMMC_TRB *Trb\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_COMMAND_PACKET *Packet;\r
- UINT64 Timeout;\r
- BOOLEAN InfiniteWait;\r
+ EFI_STATUS Status;\r
+ EMMC_COMMAND_PACKET *Packet;\r
+ UINT64 Timeout;\r
+ BOOLEAN InfiniteWait;\r
\r
//\r
// Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
if (Status != EFI_NOT_READY) {\r
return Status;\r
}\r
+\r
//\r
// Stall for 1 microsecond.\r
//\r
**/\r
EFI_STATUS\r
EmmcPeimExecTrb (\r
- IN UINTN Bar,\r
- IN EMMC_TRB *Trb\r
+ IN UINTN Bar,\r
+ IN EMMC_TRB *Trb\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_COMMAND_PACKET *Packet;\r
- UINT16 Cmd;\r
- UINT16 IntStatus;\r
- UINT32 Argument;\r
- UINT16 BlkCount;\r
- UINT16 BlkSize;\r
- UINT16 TransMode;\r
- UINT8 HostCtrl1;\r
- UINT32 SdmaAddr;\r
- UINT64 AdmaAddr;\r
+ EFI_STATUS Status;\r
+ EMMC_COMMAND_PACKET *Packet;\r
+ UINT16 Cmd;\r
+ UINT16 IntStatus;\r
+ UINT32 Argument;\r
+ UINT16 BlkCount;\r
+ UINT16 BlkSize;\r
+ UINT16 TransMode;\r
+ UINT8 HostCtrl1;\r
+ UINT32 SdmaAddr;\r
+ UINT64 AdmaAddr;\r
\r
Packet = Trb->Packet;\r
//\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Clear all bits in Normal Interrupt Status Register\r
//\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Set Host Control 1 register DMA Select field\r
//\r
if (Trb->Mode == EmmcAdmaMode) {\r
HostCtrl1 = BIT4;\r
- Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
+ Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);\r
}\r
\r
- Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
if (Trb->Mode != EmmcPioMode) {\r
TransMode |= BIT0;\r
}\r
+\r
if (Trb->Read) {\r
TransMode |= BIT4;\r
}\r
+\r
if (BlkCount > 1) {\r
TransMode |= BIT5 | BIT1;\r
}\r
return Status;\r
}\r
\r
- Cmd = (UINT16)LShiftU64(Packet->EmmcCmdBlk->CommandIndex, 8);\r
+ Cmd = (UINT16)LShiftU64 (Packet->EmmcCmdBlk->CommandIndex, 8);\r
if (Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) {\r
Cmd |= BIT5;\r
}\r
+\r
//\r
// Convert ResponseType to value\r
//\r
break;\r
case EmmcResponceTypeR2:\r
Cmd |= (BIT0 | BIT3);\r
- break;\r
+ break;\r
case EmmcResponceTypeR3:\r
case EmmcResponceTypeR4:\r
Cmd |= BIT1;\r
break;\r
}\r
}\r
+\r
//\r
// Execute cmd\r
//\r
**/\r
EFI_STATUS\r
EmmcPeimCheckTrbResult (\r
- IN UINTN Bar,\r
- IN EMMC_TRB *Trb\r
+ IN UINTN Bar,\r
+ IN EMMC_TRB *Trb\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_COMMAND_PACKET *Packet;\r
- UINT16 IntStatus;\r
- UINT32 Response[4];\r
- UINT32 SdmaAddr;\r
- UINT8 Index;\r
- UINT8 SwReset;\r
- UINT32 PioLength;\r
+ EFI_STATUS Status;\r
+ EMMC_COMMAND_PACKET *Packet;\r
+ UINT16 IntStatus;\r
+ UINT32 Response[4];\r
+ UINT32 SdmaAddr;\r
+ UINT8 Index;\r
+ UINT8 SwReset;\r
+ UINT32 PioLength;\r
\r
SwReset = 0;\r
Packet = Trb->Packet;\r
if (EFI_ERROR (Status)) {\r
goto Done;\r
}\r
+\r
//\r
// Check Transfer Complete bit is set or not.\r
//\r
\r
goto Done;\r
}\r
+\r
//\r
// Check if there is a error happened during cmd execution.\r
// If yes, then do error recovery procedure to follow SD Host Controller\r
if ((IntStatus & 0x0F) != 0) {\r
SwReset |= BIT1;\r
}\r
+\r
if ((IntStatus & 0xF0) != 0) {\r
SwReset |= BIT2;\r
}\r
if (EFI_ERROR (Status)) {\r
goto Done;\r
}\r
+\r
Status = EmmcPeimHcWaitMmioSet (\r
Bar + EMMC_HC_SW_RST,\r
sizeof (SwReset),\r
Status = EFI_DEVICE_ERROR;\r
goto Done;\r
}\r
+\r
//\r
// Check if DMA interrupt is signalled for the SDMA transfer.\r
//\r
if (EFI_ERROR (Status)) {\r
goto Done;\r
}\r
+\r
//\r
// Update SDMA Address register.\r
//\r
if (EFI_ERROR (Status)) {\r
goto Done;\r
}\r
+\r
Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;\r
}\r
\r
if ((Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeAdtc) &&\r
(Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR1b) &&\r
- (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR5b)) {\r
+ (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR5b))\r
+ {\r
if ((IntStatus & BIT0) == BIT0) {\r
Status = EFI_SUCCESS;\r
goto Done;\r
// Read data out from Buffer Port register\r
//\r
for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {\r
- EmmcPeimHcRwMmio (Bar + EMMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);\r
+ EmmcPeimHcRwMmio (Bar + EMMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8 *)Trb->Data + PioLength);\r
}\r
+\r
Status = EFI_SUCCESS;\r
goto Done;\r
}\r
return Status;\r
}\r
}\r
+\r
CopyMem (Packet->EmmcStatusBlk, Response, sizeof (Response));\r
}\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimWaitTrbResult (\r
- IN UINTN Bar,\r
- IN EMMC_TRB *Trb\r
+ IN UINTN Bar,\r
+ IN EMMC_TRB *Trb\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_COMMAND_PACKET *Packet;\r
- UINT64 Timeout;\r
- BOOLEAN InfiniteWait;\r
+ EFI_STATUS Status;\r
+ EMMC_COMMAND_PACKET *Packet;\r
+ UINT64 Timeout;\r
+ BOOLEAN InfiniteWait;\r
\r
Packet = Trb->Packet;\r
//\r
if (Status != EFI_NOT_READY) {\r
return Status;\r
}\r
+\r
//\r
// Stall for 1 microsecond.\r
//\r
EFI_STATUS\r
EFIAPI\r
EmmcPeimExecCmd (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN OUT EMMC_COMMAND_PACKET *Packet\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN OUT EMMC_COMMAND_PACKET *Packet\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_TRB *Trb;\r
+ EFI_STATUS Status;\r
+ EMMC_TRB *Trb;\r
\r
if (Packet == NULL) {\r
return EFI_INVALID_PARAMETER;\r
**/\r
EFI_STATUS\r
EmmcPeimReset (\r
- IN EMMC_PEIM_HC_SLOT *Slot\r
+ IN EMMC_PEIM_HC_SLOT *Slot\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeBc;\r
- EmmcCmdBlk.ResponseType = 0;\r
+ EmmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeBc;\r
+ EmmcCmdBlk.ResponseType = 0;\r
EmmcCmdBlk.CommandArgument = 0;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimGetOcr (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN OUT UINT32 *Argument\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN OUT UINT32 *Argument\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR3;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR3;\r
EmmcCmdBlk.CommandArgument = *Argument;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimGetAllCid (\r
- IN EMMC_PEIM_HC_SLOT *Slot\r
+ IN EMMC_PEIM_HC_SLOT *Slot\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
+ EmmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
EmmcCmdBlk.CommandArgument = 0;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimSetRca (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimGetCsd (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca,\r
- OUT EMMC_CSD *Csd\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca,\r
+ OUT EMMC_CSD *Csd\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SEND_CSD;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_CSD;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
//\r
// For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r
//\r
- CopyMem (((UINT8*)Csd) + 1, &EmmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);\r
+ CopyMem (((UINT8 *)Csd) + 1, &EmmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);\r
}\r
\r
return Status;\r
**/\r
EFI_STATUS\r
EmmcPeimSelect (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimGetExtCsd (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- OUT EMMC_EXT_CSD *ExtCsd\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ OUT EMMC_EXT_CSD *ExtCsd\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
EmmcCmdBlk.CommandArgument = 0x00000000;\r
\r
Packet.InDataBuffer = ExtCsd;\r
**/\r
EFI_STATUS\r
EmmcPeimSwitch (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT8 Access,\r
- IN UINT8 Index,\r
- IN UINT8 Value,\r
- IN UINT8 CmdSet\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT8 Access,\r
+ IN UINT8 Index,\r
+ IN UINT8 Value,\r
+ IN UINT8 CmdSet\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SWITCH;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR1b;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SWITCH;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1b;\r
EmmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimSendStatus (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca,\r
- OUT UINT32 *DevStatus\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca,\r
+ OUT UINT32 *DevStatus\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
EmmcCmdBlk.CommandArgument = Rca << 16;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimSetBlkCount (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT16 BlockCount\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT16 BlockCount\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SET_BLOCK_COUNT;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SET_BLOCK_COUNT;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
EmmcCmdBlk.CommandArgument = BlockCount;\r
\r
Status = EmmcPeimExecCmd (Slot, &Packet);\r
**/\r
EFI_STATUS\r
EmmcPeimRwMultiBlocks (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN EFI_LBA Lba,\r
- IN UINT32 BlockSize,\r
- IN VOID *Buffer,\r
- IN UINTN BufferSize,\r
- IN BOOLEAN IsRead\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN EFI_LBA Lba,\r
+ IN UINT32 BlockSize,\r
+ IN VOID *Buffer,\r
+ IN UINTN BufferSize,\r
+ IN BOOLEAN IsRead\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
// transfer speed (2.4MB/s).\r
// Refer to eMMC 5.0 spec section 6.9.1 for details.\r
//\r
- Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;\r
+ Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;\r
\r
if (IsRead) {\r
Packet.InDataBuffer = Buffer;\r
**/\r
EFI_STATUS\r
EmmcPeimSendTuningBlk (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT8 BusWidth\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT8 BusWidth\r
)\r
{\r
- EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
- EMMC_STATUS_BLOCK EmmcStatusBlk;\r
- EMMC_COMMAND_PACKET Packet;\r
- EFI_STATUS Status;\r
- UINT8 TuningBlock[128];\r
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
+ EMMC_STATUS_BLOCK EmmcStatusBlk;\r
+ EMMC_COMMAND_PACKET Packet;\r
+ EFI_STATUS Status;\r
+ UINT8 TuningBlock[128];\r
\r
ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
\r
Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
- Packet.Timeout = EMMC_TIMEOUT;\r
+ Packet.Timeout = EMMC_TIMEOUT;\r
\r
- EmmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;\r
- EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
- EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;\r
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
EmmcCmdBlk.CommandArgument = 0;\r
\r
Packet.InDataBuffer = TuningBlock;\r
**/\r
EFI_STATUS\r
EmmcPeimTuningClkForHs200 (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT8 BusWidth\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT8 BusWidth\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HostCtrl2;\r
- UINT8 Retry;\r
+ EFI_STATUS Status;\r
+ UINT8 HostCtrl2;\r
+ UINT8 Retry;\r
\r
//\r
// Notify the host that the sampling clock tuning procedure starts.\r
//\r
HostCtrl2 = BIT6;\r
- Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Ask the device to send a sequence of tuning blocks till the tuning procedure is done.\r
//\r
//\r
// Abort the tuning procedure and reset the tuning circuit.\r
//\r
- HostCtrl2 = (UINT8)~(BIT6 | BIT7);\r
- Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ HostCtrl2 = (UINT8) ~(BIT6 | BIT7);\r
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
return EFI_DEVICE_ERROR;\r
}\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchBusWidth (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca,\r
- IN BOOLEAN IsDdr,\r
- IN UINT8 BusWidth\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca,\r
+ IN BOOLEAN IsDdr,\r
+ IN UINT8 BusWidth\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 Access;\r
- UINT8 Index;\r
- UINT8 Value;\r
- UINT8 CmdSet;\r
- UINT32 DevStatus;\r
+ EFI_STATUS Status;\r
+ UINT8 Access;\r
+ UINT8 Index;\r
+ UINT8 Value;\r
+ UINT8 CmdSet;\r
+ UINT32 DevStatus;\r
\r
//\r
// Write Byte, the Value field is written into the byte pointed by Index.\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Check the switch operation is really successful or not.\r
//\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchClockFreq (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca,\r
- IN UINT8 HsTiming,\r
- IN UINT32 ClockFreq\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca,\r
+ IN UINT8 HsTiming,\r
+ IN UINT32 ClockFreq\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 Access;\r
- UINT8 Index;\r
- UINT8 Value;\r
- UINT8 CmdSet;\r
- UINT32 DevStatus;\r
+ EFI_STATUS Status;\r
+ UINT8 Access;\r
+ UINT8 Index;\r
+ UINT8 Value;\r
+ UINT8 CmdSet;\r
+ UINT32 DevStatus;\r
\r
//\r
// Write Byte, the Value field is written into the byte pointed by Index.\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Check the switch operation is really successful or not.\r
//\r
if ((DevStatus & BIT7) != 0) {\r
return EFI_DEVICE_ERROR;\r
}\r
+\r
//\r
// Convert the clock freq unit from MHz to KHz.\r
//\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchToHighSpeed (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca,\r
- IN UINT32 ClockFreq,\r
- IN BOOLEAN IsDdr,\r
- IN UINT8 BusWidth\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca,\r
+ IN UINT32 ClockFreq,\r
+ IN BOOLEAN IsDdr,\r
+ IN UINT8 BusWidth\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HsTiming;\r
- UINT8 HostCtrl1;\r
- UINT8 HostCtrl2;\r
+ EFI_STATUS Status;\r
+ UINT8 HsTiming;\r
+ UINT8 HostCtrl1;\r
+ UINT8 HostCtrl2;\r
\r
Status = EmmcPeimSwitchBusWidth (Slot, Rca, IsDdr, BusWidth);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Set to High Speed timing\r
//\r
HostCtrl1 = BIT2;\r
- Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- HostCtrl2 = (UINT8)~0x7;\r
- Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ HostCtrl2 = (UINT8) ~0x7;\r
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
if (IsDdr) {\r
HostCtrl2 = BIT2;\r
} else if (ClockFreq == 52) {\r
} else {\r
HostCtrl2 = 0;\r
}\r
+\r
Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
HsTiming = 1;\r
- Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchToHS200 (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca,\r
- IN UINT32 ClockFreq,\r
- IN UINT8 BusWidth\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca,\r
+ IN UINT32 ClockFreq,\r
+ IN UINT8 BusWidth\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HsTiming;\r
- UINT8 HostCtrl2;\r
- UINT16 ClockCtrl;\r
+ EFI_STATUS Status;\r
+ UINT8 HsTiming;\r
+ UINT8 HostCtrl2;\r
+ UINT16 ClockCtrl;\r
\r
if ((BusWidth != 4) && (BusWidth != 8)) {\r
return EFI_INVALID_PARAMETER;\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Set to HS200/SDR104 timing\r
//\r
return Status;\r
}\r
\r
- HostCtrl2 = (UINT8)~0x7;\r
- Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ HostCtrl2 = (UINT8) ~0x7;\r
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
HostCtrl2 = BIT0 | BIT1;\r
- Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Set SD Clock Enable in the Clock Control register to 1\r
//\r
ClockCtrl = BIT2;\r
- Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
\r
HsTiming = 2;\r
- Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimSwitchToHS400 (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca,\r
- IN UINT32 ClockFreq\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca,\r
+ IN UINT32 ClockFreq\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT8 HsTiming;\r
- UINT8 HostCtrl2;\r
+ EFI_STATUS Status;\r
+ UINT8 HsTiming;\r
+ UINT8 HostCtrl2;\r
\r
Status = EmmcPeimSwitchToHS200 (Slot, Rca, ClockFreq, 8);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Set to High Speed timing and set the clock frequency to a value less than 52MHz.\r
//\r
HsTiming = 1;\r
- Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, 52);\r
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, 52);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// HS400 mode must use 8 data lines.\r
//\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
//\r
// Set to HS400 timing\r
//\r
- HostCtrl2 = (UINT8)~0x7;\r
- Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ HostCtrl2 = (UINT8) ~0x7;\r
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
HostCtrl2 = BIT0 | BIT2;\r
- Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
HsTiming = 3;\r
- Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
\r
return Status;\r
}\r
**/\r
EFI_STATUS\r
EmmcPeimSetBusMode (\r
- IN EMMC_PEIM_HC_SLOT *Slot,\r
- IN UINT32 Rca\r
+ IN EMMC_PEIM_HC_SLOT *Slot,\r
+ IN UINT32 Rca\r
)\r
{\r
- EFI_STATUS Status;\r
- EMMC_HC_SLOT_CAP Capability;\r
- UINT8 HsTiming;\r
- BOOLEAN IsDdr;\r
- UINT32 ClockFreq;\r
- UINT8 BusWidth;\r
+ EFI_STATUS Status;\r
+ EMMC_HC_SLOT_CAP Capability;\r
+ UINT8 HsTiming;\r
+ BOOLEAN IsDdr;\r
+ UINT32 ClockFreq;\r
+ UINT8 BusWidth;\r
\r
Status = EmmcPeimGetCsd (Slot, Rca, &Slot->Csd);\r
if (EFI_ERROR (Status)) {\r
} else {\r
BusWidth = 4;\r
}\r
+\r
//\r
// Get Device_Type from EXT_CSD register.\r
//\r
DEBUG ((DEBUG_ERROR, "EmmcPeimSetBusMode: EmmcPeimGetExtCsd fails with %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
// Calculate supported bus speed/bus width/clock frequency.\r
//\r
IsDdr = FALSE;\r
ClockFreq = 26;\r
}\r
+\r
//\r
// Check if both of the device and the host controller support HS400 DDR mode.\r
//\r
return EFI_SUCCESS;\r
}\r
\r
- DEBUG ((DEBUG_INFO, "HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));\r
+ DEBUG ((DEBUG_INFO, "HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE" : "FALSE"));\r
\r
if (HsTiming == 3) {\r
//\r
**/\r
EFI_STATUS\r
EmmcPeimIdentification (\r
- IN EMMC_PEIM_HC_SLOT *Slot\r
+ IN EMMC_PEIM_HC_SLOT *Slot\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 Ocr;\r
- UINT32 Rca;\r
- UINTN Retry;\r
+ EFI_STATUS Status;\r
+ UINT32 Ocr;\r
+ UINT32 Rca;\r
+ UINTN Retry;\r
\r
Status = EmmcPeimReset (Slot);\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_ERROR, "EmmcPeimIdentification: EmmcPeimGetOcr fails too many times\n"));\r
return EFI_DEVICE_ERROR;\r
}\r
+\r
MicroSecondDelay (10 * 1000);\r
} while ((Ocr & BIT31) == 0);\r
\r
DEBUG ((DEBUG_ERROR, "EmmcPeimIdentification: EmmcPeimGetAllCid fails with %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
// Don't support multiple devices on the slot, that is\r
// shared bus slot feature.\r
DEBUG ((DEBUG_ERROR, "EmmcPeimIdentification: EmmcPeimSetRca fails with %r\n", Status));\r
return Status;\r
}\r
+\r
//\r
// Enter Data Tranfer Mode.\r
//\r
projects / mirror_edk2.git / blobdiff