--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SD_HCI_H_\r
+#define _SD_HCI_H_\r
+\r
+//\r
+// SD Host Controller MMIO Register Offset\r
+//\r
+#define SD_HC_SDMA_ADDR 0x00\r
+#define SD_HC_ARG2 0x00\r
+#define SD_HC_BLK_SIZE 0x04\r
+#define SD_HC_BLK_COUNT 0x06\r
+#define SD_HC_ARG1 0x08\r
+#define SD_HC_TRANS_MOD 0x0C\r
+#define SD_HC_COMMAND 0x0E\r
+#define SD_HC_RESPONSE 0x10\r
+#define SD_HC_BUF_DAT_PORT 0x20\r
+#define SD_HC_PRESENT_STATE 0x24\r
+#define SD_HC_HOST_CTRL1 0x28\r
+#define SD_HC_POWER_CTRL 0x29\r
+#define SD_HC_BLK_GAP_CTRL 0x2A\r
+#define SD_HC_WAKEUP_CTRL 0x2B\r
+#define SD_HC_CLOCK_CTRL 0x2C\r
+#define SD_HC_TIMEOUT_CTRL 0x2E\r
+#define SD_HC_SW_RST 0x2F\r
+#define SD_HC_NOR_INT_STS 0x30\r
+#define SD_HC_ERR_INT_STS 0x32\r
+#define SD_HC_NOR_INT_STS_EN 0x34\r
+#define SD_HC_ERR_INT_STS_EN 0x36\r
+#define SD_HC_NOR_INT_SIG_EN 0x38\r
+#define SD_HC_ERR_INT_SIG_EN 0x3A\r
+#define SD_HC_AUTO_CMD_ERR_STS 0x3C\r
+#define SD_HC_HOST_CTRL2 0x3E\r
+#define SD_HC_CAP 0x40\r
+#define SD_HC_MAX_CURRENT_CAP 0x48\r
+#define SD_HC_FORCE_EVT_AUTO_CMD 0x50\r
+#define SD_HC_FORCE_EVT_ERR_INT 0x52\r
+#define SD_HC_ADMA_ERR_STS 0x54\r
+#define SD_HC_ADMA_SYS_ADDR 0x58\r
+#define SD_HC_PRESET_VAL 0x60\r
+#define SD_HC_SHARED_BUS_CTRL 0xE0\r
+#define SD_HC_SLOT_INT_STS 0xFC\r
+#define SD_HC_CTRL_VER 0xFE\r
+\r
+//\r
+// The transfer modes supported by SD Host Controller\r
+// Simplified Spec 3.0 Table 1-2\r
+//\r
+typedef enum {\r
+ SdNoData,\r
+ SdPioMode,\r
+ SdSdmaMode,\r
+ SdAdmaMode\r
+} SD_HC_TRANSFER_MODE;\r
+\r
+//\r
+// The maximum data length of each descriptor line\r
+//\r
+#define ADMA_MAX_DATA_PER_LINE 0x10000\r
+#define SD_SDMA_BOUNDARY 512 * 1024\r
+#define SD_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
+\r
+typedef enum {\r
+ SdCommandTypeBc, // Broadcast commands, no response\r
+ SdCommandTypeBcr, // Broadcast commands with response\r
+ SdCommandTypeAc, // Addressed(point-to-point) commands\r
+ SdCommandTypeAdtc // Addressed(point-to-point) data transfer commands\r
+} SD_COMMAND_TYPE;\r
+\r
+typedef enum {\r
+ SdResponseTypeR1,\r
+ SdResponseTypeR1b,\r
+ SdResponseTypeR2,\r
+ SdResponseTypeR3,\r
+ SdResponseTypeR4,\r
+ SdResponseTypeR5,\r
+ SdResponseTypeR5b,\r
+ SdResponseTypeR6,\r
+ SdResponseTypeR7\r
+} SD_RESPONSE_TYPE;\r
+\r
+typedef struct _SD_COMMAND_BLOCK {\r
+ UINT16 CommandIndex;\r
+ UINT32 CommandArgument;\r
+ UINT32 CommandType; // One of the SD_COMMAND_TYPE values\r
+ UINT32 ResponseType; // One of the SD_RESPONSE_TYPE values\r
+} SD_COMMAND_BLOCK;\r
+\r
+typedef struct _SD_STATUS_BLOCK {\r
+ UINT32 Resp0;\r
+ UINT32 Resp1;\r
+ UINT32 Resp2;\r
+ UINT32 Resp3;\r
+} SD_STATUS_BLOCK;\r
+\r
+typedef struct _SD_COMMAND_PACKET {\r
+ UINT64 Timeout;\r
+ SD_COMMAND_BLOCK *SdCmdBlk;\r
+ SD_STATUS_BLOCK *SdStatusBlk;\r
+ VOID *InDataBuffer;\r
+ VOID *OutDataBuffer;\r
+ UINT32 InTransferLength;\r
+ UINT32 OutTransferLength;\r
+} SD_COMMAND_PACKET;\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ UINT32 Valid:1;\r
+ UINT32 End:1;\r
+ UINT32 Int:1;\r
+ UINT32 Reserved:1;\r
+ UINT32 Act:2;\r
+ UINT32 Reserved1:10;\r
+ UINT32 Length:16;\r
+ UINT32 Address;\r
+} SD_HC_ADMA_DESC_LINE;\r
+\r
+typedef struct {\r
+ UINT32 TimeoutFreq:6; // bit 0:5\r
+ UINT32 Reserved:1; // bit 6\r
+ UINT32 TimeoutUnit:1; // bit 7\r
+ UINT32 BaseClkFreq:8; // bit 8:15\r
+ UINT32 MaxBlkLen:2; // bit 16:17\r
+ UINT32 BusWidth8:1; // bit 18\r
+ UINT32 Adma2:1; // bit 19\r
+ UINT32 Reserved2:1; // bit 20\r
+ UINT32 HighSpeed:1; // bit 21\r
+ UINT32 Sdma:1; // bit 22\r
+ UINT32 SuspRes:1; // bit 23\r
+ UINT32 Voltage33:1; // bit 24\r
+ UINT32 Voltage30:1; // bit 25\r
+ UINT32 Voltage18:1; // bit 26\r
+ UINT32 Reserved3:1; // bit 27\r
+ UINT32 SysBus64:1; // bit 28\r
+ UINT32 AsyncInt:1; // bit 29\r
+ UINT32 SlotType:2; // bit 30:31\r
+ UINT32 Sdr50:1; // bit 32\r
+ UINT32 Sdr104:1; // bit 33\r
+ UINT32 Ddr50:1; // bit 34\r
+ UINT32 Reserved4:1; // bit 35\r
+ UINT32 DriverTypeA:1; // bit 36\r
+ UINT32 DriverTypeC:1; // bit 37\r
+ UINT32 DriverTypeD:1; // bit 38\r
+ UINT32 DriverType4:1; // bit 39\r
+ UINT32 TimerCount:4; // bit 40:43\r
+ UINT32 Reserved5:1; // bit 44\r
+ UINT32 TuningSDR50:1; // bit 45\r
+ UINT32 RetuningMod:2; // bit 46:47\r
+ UINT32 ClkMultiplier:8; // bit 48:55\r
+ UINT32 Reserved6:7; // bit 56:62\r
+ UINT32 Hs400:1; // bit 63\r
+} SD_HC_SLOT_CAP;\r
+\r
+#pragma pack()\r
+\r
+/**\r
+ Software reset the specified SD host controller and enable all interrupts.\r
+\r
+ @param[in] Bar The mmio base address of the slot to be accessed.\r
+\r
+ @retval EFI_SUCCESS The software reset executes successfully.\r
+ @retval Others The software reset fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimHcReset (\r
+ IN UINTN Bar\r
+ );\r
+\r
+/**\r
+ Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
+ register.\r
+\r
+ @param[in] Bar The mmio base address of the slot to be accessed.\r
+\r
+ @retval EFI_SUCCESS The operation executes successfully.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimHcEnableInterrupt (\r
+ IN UINTN Bar\r
+ );\r
+\r
+/**\r
+ Get the capability data from the specified slot.\r
+\r
+ @param[in] Bar The mmio base address of the slot to be accessed.\r
+ @param[out] Capability The buffer to store the capability data.\r
+\r
+ @retval EFI_SUCCESS The operation executes successfully.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimHcGetCapability (\r
+ IN UINTN Bar,\r
+ OUT SD_HC_SLOT_CAP *Capability\r
+ );\r
+\r
+/**\r
+ Detect whether there is a SD card attached at the specified SD host controller\r
+ slot.\r
+\r
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
+\r
+ @param[in] Bar The mmio base address of the slot to be accessed.\r
+\r
+ @retval EFI_SUCCESS There is a SD card attached.\r
+ @retval EFI_NO_MEDIA There is not a SD card attached.\r
+ @retval Others The detection fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimHcCardDetect (\r
+ IN UINTN Bar\r
+ );\r
+\r
+/**\r
+ Initial SD host controller with lowest clock frequency, max power and max timeout value\r
+ at initialization.\r
+\r
+ @param[in] Bar The mmio base address of the slot to be accessed.\r
+\r
+ @retval EFI_SUCCESS The host controller is initialized successfully.\r
+ @retval Others The host controller isn't initialized successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimHcInitHost (\r
+ IN UINTN Bar\r
+ );\r
+\r
+/**\r
+ Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.\r
+\r
+ Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
+\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[in] AccessMode The value for access mode group.\r
+ @param[in] CommandSystem The value for command set group.\r
+ @param[in] DriveStrength The value for drive length group.\r
+ @param[in] PowerLimit The value for power limit group.\r
+ @param[in] Mode Switch or check function.\r
+\r
+ @retval EFI_SUCCESS The operation is done correctly.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimSwitch (\r
+ IN SD_PEIM_HC_SLOT *Slot,\r
+ IN UINT8 AccessMode,\r
+ IN UINT8 CommandSystem,\r
+ IN UINT8 DriveStrength,\r
+ IN UINT8 PowerLimit,\r
+ IN BOOLEAN Mode\r
+ );\r
+\r
+/**\r
+ Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device\r
+ to read/write the specified number of blocks.\r
+\r
+ Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
+\r
+ @param[in] Slot The slot number of the SD card to send the command to.\r
+ @param[in] Lba The logical block address of starting access.\r
+ @param[in] BlockSize The block size of specified SD device partition.\r
+ @param[in] Buffer The pointer to the transfer buffer.\r
+ @param[in] BufferSize The size of transfer buffer.\r
+ @param[in] IsRead Boolean to show the operation direction.\r
+\r
+ @retval EFI_SUCCESS The operation is done correctly.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimRwSingleBlock (\r
+ IN SD_PEIM_HC_SLOT *Slot,\r
+ IN EFI_LBA Lba,\r
+ IN UINT32 BlockSize,\r
+ IN VOID *Buffer,\r
+ IN UINTN BufferSize,\r
+ IN BOOLEAN IsRead\r
+ );\r
+\r
+/**\r
+ Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device\r
+ to read/write the specified number of blocks.\r
+\r
+ Refer to SD Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
+\r
+ @param[in] Slot The slot number of the Sd card to send the command to.\r
+ @param[in] Lba The logical block address of starting access.\r
+ @param[in] BlockSize The block size of specified SD device partition.\r
+ @param[in] Buffer The pointer to the transfer buffer.\r
+ @param[in] BufferSize The size of transfer buffer.\r
+ @param[in] IsRead Boolean to show the operation direction.\r
+\r
+ @retval EFI_SUCCESS The operation is done correctly.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimRwMultiBlocks (\r
+ IN SD_PEIM_HC_SLOT *Slot,\r
+ IN EFI_LBA Lba,\r
+ IN UINT32 BlockSize,\r
+ IN VOID *Buffer,\r
+ IN UINTN BufferSize,\r
+ IN BOOLEAN IsRead\r
+ );\r
+\r
+/**\r
+ Execute SD device identification procedure.\r
+\r
+ Refer to SD Electrical Standard Spec 5.1 Section 6.4 for details.\r
+\r
+ @param[in] Slot The slot number of the Sd card to send the command to.\r
+\r
+ @retval EFI_SUCCESS There is a SD card.\r
+ @retval Others There is not a SD card.\r
+\r
+**/\r
+EFI_STATUS\r
+SdPeimIdentification (\r
+ IN SD_PEIM_HC_SLOT *Slot\r
+ );\r
+\r
+/**\r
+ Free the resource used by the TRB.\r
+\r
+ @param[in] Trb The pointer to the SD_TRB instance.\r
+\r
+**/\r
+VOID\r
+SdPeimFreeTrb (\r
+ IN SD_TRB *Trb\r
+ );\r
+\r
+#endif\r
+\r
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