//\r
// Host Capabilities Register Offsets\r
//\r
-#define UFS_HC_CAP_OFFSET 0x0000 // Controller Capabilities\r
-#define UFS_HC_VER_OFFSET 0x0008 // Version\r
-#define UFS_HC_DDID_OFFSET 0x0010 // Device ID and Device Class\r
-#define UFS_HC_PMID_OFFSET 0x0014 // Product ID and Manufacturer ID\r
-#define UFS_HC_AHIT_OFFSET 0x0018 // Auto-Hibernate Idle Timer\r
+#define UFS_HC_CAP_OFFSET 0x0000 // Controller Capabilities\r
+#define UFS_HC_VER_OFFSET 0x0008 // Version\r
+#define UFS_HC_DDID_OFFSET 0x0010 // Device ID and Device Class\r
+#define UFS_HC_PMID_OFFSET 0x0014 // Product ID and Manufacturer ID\r
+#define UFS_HC_AHIT_OFFSET 0x0018 // Auto-Hibernate Idle Timer\r
//\r
// Operation and Runtime Register Offsets\r
//\r
-#define UFS_HC_IS_OFFSET 0x0020 // Interrupt Status\r
-#define UFS_HC_IE_OFFSET 0x0024 // Interrupt Enable\r
-#define UFS_HC_STATUS_OFFSET 0x0030 // Host Controller Status\r
-#define UFS_HC_ENABLE_OFFSET 0x0034 // Host Controller Enable\r
-#define UFS_HC_UECPA_OFFSET 0x0038 // Host UIC Error Code PHY Adapter Layer\r
-#define UFS_HC_UECDL_OFFSET 0x003c // Host UIC Error Code Data Link Layer\r
-#define UFS_HC_UECN_OFFSET 0x0040 // Host UIC Error Code Network Layer\r
-#define UFS_HC_UECT_OFFSET 0x0044 // Host UIC Error Code Transport Layer\r
-#define UFS_HC_UECDME_OFFSET 0x0048 // Host UIC Error Code DME\r
-#define UFS_HC_UTRIACR_OFFSET 0x004c // UTP Transfer Request Interrupt Aggregation Control Register\r
+#define UFS_HC_IS_OFFSET 0x0020 // Interrupt Status\r
+#define UFS_HC_IE_OFFSET 0x0024 // Interrupt Enable\r
+#define UFS_HC_STATUS_OFFSET 0x0030 // Host Controller Status\r
+#define UFS_HC_ENABLE_OFFSET 0x0034 // Host Controller Enable\r
+#define UFS_HC_UECPA_OFFSET 0x0038 // Host UIC Error Code PHY Adapter Layer\r
+#define UFS_HC_UECDL_OFFSET 0x003c // Host UIC Error Code Data Link Layer\r
+#define UFS_HC_UECN_OFFSET 0x0040 // Host UIC Error Code Network Layer\r
+#define UFS_HC_UECT_OFFSET 0x0044 // Host UIC Error Code Transport Layer\r
+#define UFS_HC_UECDME_OFFSET 0x0048 // Host UIC Error Code DME\r
+#define UFS_HC_UTRIACR_OFFSET 0x004c // UTP Transfer Request Interrupt Aggregation Control Register\r
//\r
// UTP Transfer Register Offsets\r
//\r
-#define UFS_HC_UTRLBA_OFFSET 0x0050 // UTP Transfer Request List Base Address\r
-#define UFS_HC_UTRLBAU_OFFSET 0x0054 // UTP Transfer Request List Base Address Upper 32-Bits\r
-#define UFS_HC_UTRLDBR_OFFSET 0x0058 // UTP Transfer Request List Door Bell Register\r
-#define UFS_HC_UTRLCLR_OFFSET 0x005c // UTP Transfer Request List CLear Register\r
-#define UFS_HC_UTRLRSR_OFFSET 0x0060 // UTP Transfer Request Run-Stop Register\r
+#define UFS_HC_UTRLBA_OFFSET 0x0050 // UTP Transfer Request List Base Address\r
+#define UFS_HC_UTRLBAU_OFFSET 0x0054 // UTP Transfer Request List Base Address Upper 32-Bits\r
+#define UFS_HC_UTRLDBR_OFFSET 0x0058 // UTP Transfer Request List Door Bell Register\r
+#define UFS_HC_UTRLCLR_OFFSET 0x005c // UTP Transfer Request List CLear Register\r
+#define UFS_HC_UTRLRSR_OFFSET 0x0060 // UTP Transfer Request Run-Stop Register\r
//\r
// UTP Task Management Register Offsets\r
//\r
-#define UFS_HC_UTMRLBA_OFFSET 0x0070 // UTP Task Management Request List Base Address\r
-#define UFS_HC_UTMRLBAU_OFFSET 0x0074 // UTP Task Management Request List Base Address Upper 32-Bits\r
-#define UFS_HC_UTMRLDBR_OFFSET 0x0078 // UTP Task Management Request List Door Bell Register\r
-#define UFS_HC_UTMRLCLR_OFFSET 0x007c // UTP Task Management Request List CLear Register\r
-#define UFS_HC_UTMRLRSR_OFFSET 0x0080 // UTP Task Management Run-Stop Register\r
+#define UFS_HC_UTMRLBA_OFFSET 0x0070 // UTP Task Management Request List Base Address\r
+#define UFS_HC_UTMRLBAU_OFFSET 0x0074 // UTP Task Management Request List Base Address Upper 32-Bits\r
+#define UFS_HC_UTMRLDBR_OFFSET 0x0078 // UTP Task Management Request List Door Bell Register\r
+#define UFS_HC_UTMRLCLR_OFFSET 0x007c // UTP Task Management Request List CLear Register\r
+#define UFS_HC_UTMRLRSR_OFFSET 0x0080 // UTP Task Management Run-Stop Register\r
//\r
// UIC Command Register Offsets\r
//\r
-#define UFS_HC_UIC_CMD_OFFSET 0x0090 // UIC Command Register\r
-#define UFS_HC_UCMD_ARG1_OFFSET 0x0094 // UIC Command Argument 1\r
-#define UFS_HC_UCMD_ARG2_OFFSET 0x0098 // UIC Command Argument 2\r
-#define UFS_HC_UCMD_ARG3_OFFSET 0x009c // UIC Command Argument 3\r
+#define UFS_HC_UIC_CMD_OFFSET 0x0090 // UIC Command Register\r
+#define UFS_HC_UCMD_ARG1_OFFSET 0x0094 // UIC Command Argument 1\r
+#define UFS_HC_UCMD_ARG2_OFFSET 0x0098 // UIC Command Argument 2\r
+#define UFS_HC_UCMD_ARG3_OFFSET 0x009c // UIC Command Argument 3\r
//\r
// UMA Register Offsets\r
//\r
-#define UFS_HC_UMA_OFFSET 0x00b0 // Reserved for Unified Memory Extension\r
+#define UFS_HC_UMA_OFFSET 0x00b0 // Reserved for Unified Memory Extension\r
\r
-#define UFS_HC_HCE_EN BIT0\r
-#define UFS_HC_HCS_DP BIT0\r
-#define UFS_HC_HCS_UCRDY BIT3\r
-#define UFS_HC_IS_ULSS BIT8\r
-#define UFS_HC_IS_UCCS BIT10\r
-#define UFS_HC_CAP_64ADDR BIT24\r
-#define UFS_HC_CAP_NUTMRS (BIT16 | BIT17 | BIT18)\r
-#define UFS_HC_CAP_NUTRS (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)\r
-#define UFS_HC_UTMRLRSR BIT0\r
-#define UFS_HC_UTRLRSR BIT0\r
+#define UFS_HC_HCE_EN BIT0\r
+#define UFS_HC_HCS_DP BIT0\r
+#define UFS_HC_HCS_UCRDY BIT3\r
+#define UFS_HC_IS_ULSS BIT8\r
+#define UFS_HC_IS_UCCS BIT10\r
+#define UFS_HC_CAP_64ADDR BIT24\r
+#define UFS_HC_CAP_NUTMRS (BIT16 | BIT17 | BIT18)\r
+#define UFS_HC_CAP_NUTRS (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)\r
+#define UFS_HC_UTMRLRSR BIT0\r
+#define UFS_HC_UTRLRSR BIT0\r
\r
//\r
// The initial value of the OCS field of UTP TRD or TMRD descriptor\r
//\r
// A maximum of length of 256KB is supported by PRDT entry\r
//\r
-#define UFS_MAX_DATA_LEN_PER_PRD 0x40000\r
+#define UFS_MAX_DATA_LEN_PER_PRD 0x40000\r
\r
-#define UFS_STORAGE_COMMAND_TYPE 0x01\r
+#define UFS_STORAGE_COMMAND_TYPE 0x01\r
\r
-#define UFS_REGULAR_COMMAND 0x00\r
-#define UFS_INTERRUPT_COMMAND 0x01\r
+#define UFS_REGULAR_COMMAND 0x00\r
+#define UFS_INTERRUPT_COMMAND 0x01\r
\r
-#define UFS_LUN_0 0x00\r
-#define UFS_LUN_1 0x01\r
-#define UFS_LUN_2 0x02\r
-#define UFS_LUN_3 0x03\r
-#define UFS_LUN_4 0x04\r
-#define UFS_LUN_5 0x05\r
-#define UFS_LUN_6 0x06\r
-#define UFS_LUN_7 0x07\r
-#define UFS_WLUN_REPORT_LUNS 0x81\r
-#define UFS_WLUN_UFS_DEV 0xD0\r
-#define UFS_WLUN_BOOT 0xB0\r
-#define UFS_WLUN_RPMB 0xC4\r
+#define UFS_LUN_0 0x00\r
+#define UFS_LUN_1 0x01\r
+#define UFS_LUN_2 0x02\r
+#define UFS_LUN_3 0x03\r
+#define UFS_LUN_4 0x04\r
+#define UFS_LUN_5 0x05\r
+#define UFS_LUN_6 0x06\r
+#define UFS_LUN_7 0x07\r
+#define UFS_WLUN_REPORT_LUNS 0x81\r
+#define UFS_WLUN_UFS_DEV 0xD0\r
+#define UFS_WLUN_BOOT 0xB0\r
+#define UFS_WLUN_RPMB 0xC4\r
\r
#pragma pack(1)\r
\r
// UFSHCI 2.0 Spec Section 5.2.1 Offset 00h: CAP - Controller Capabilities\r
//\r
typedef struct {\r
- UINT8 Nutrs:4; // Number of UTP Transfer Request Slots\r
- UINT8 Rsvd1:4;\r
+ UINT8 Nutrs : 4; // Number of UTP Transfer Request Slots\r
+ UINT8 Rsvd1 : 4;\r
\r
- UINT8 NoRtt; // Number of outstanding READY TO TRANSFER (RTT) requests supported\r
+ UINT8 NoRtt; // Number of outstanding READY TO TRANSFER (RTT) requests supported\r
\r
- UINT8 Nutmrs:3; // Number of UTP Task Management Request Slots\r
- UINT8 Rsvd2:4;\r
- UINT8 AutoHs:1; // Auto-Hibernation Support\r
+ UINT8 Nutmrs : 3; // Number of UTP Task Management Request Slots\r
+ UINT8 Rsvd2 : 4;\r
+ UINT8 AutoHs : 1; // Auto-Hibernation Support\r
\r
- UINT8 As64:1; // 64-bit addressing supported\r
- UINT8 Oodds:1; // Out of order data delivery supported\r
- UINT8 UicDmetms:1; // UIC DME_TEST_MODE command supported\r
- UINT8 Ume:1; // Reserved for Unified Memory Extension\r
- UINT8 Rsvd4:4;\r
+ UINT8 As64 : 1; // 64-bit addressing supported\r
+ UINT8 Oodds : 1; // Out of order data delivery supported\r
+ UINT8 UicDmetms : 1; // UIC DME_TEST_MODE command supported\r
+ UINT8 Ume : 1; // Reserved for Unified Memory Extension\r
+ UINT8 Rsvd4 : 4;\r
} UFS_HC_CAP;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.2.2 Offset 08h: VER - UFS Version\r
//\r
typedef struct {\r
- UINT8 Vs:4; // Version Suffix\r
- UINT8 Mnr:4; // Minor version number\r
+ UINT8 Vs : 4; // Version Suffix\r
+ UINT8 Mnr : 4; // Minor version number\r
\r
- UINT8 Mjr; // Major version number\r
+ UINT8 Mjr; // Major version number\r
\r
- UINT16 Rsvd1;\r
+ UINT16 Rsvd1;\r
} UFS_HC_VER;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.2.3 Offset 10h: HCPID - Host Controller Product ID\r
//\r
-#define UFS_HC_PID UINT32\r
+#define UFS_HC_PID UINT32\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.2.4 Offset 14h: HCMID - Host Controller Manufacturer ID\r
//\r
-#define UFS_HC_MID UINT32\r
+#define UFS_HC_MID UINT32\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.2.5 Offset 18h: AHIT - Auto-Hibernate Idle Timer\r
//\r
typedef struct {\r
- UINT32 Ahitv:10; // Auto-Hibernate Idle Timer Value\r
- UINT32 Ts:3; // Timer scale\r
- UINT32 Rsvd1:19;\r
+ UINT32 Ahitv : 10; // Auto-Hibernate Idle Timer Value\r
+ UINT32 Ts : 3; // Timer scale\r
+ UINT32 Rsvd1 : 19;\r
} UFS_HC_AHIT;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.1 Offset 20h: IS - Interrupt Status\r
//\r
typedef struct {\r
- UINT16 Utrcs:1; // UTP Transfer Request Completion Status\r
- UINT16 Udepri:1; // UIC DME_ENDPOINT_RESET Indication\r
- UINT16 Ue:1; // UIC Error\r
- UINT16 Utms:1; // UIC Test Mode Status\r
-\r
- UINT16 Upms:1; // UIC Power Mode Status\r
- UINT16 Uhxs:1; // UIC Hibernate Exit Status\r
- UINT16 Uhes:1; // UIC Hibernate Enter Status\r
- UINT16 Ulls:1; // UIC Link Lost Status\r
-\r
- UINT16 Ulss:1; // UIC Link Startup Status\r
- UINT16 Utmrcs:1; // UTP Task Management Request Completion Status\r
- UINT16 Uccs:1; // UIC Command Completion Status\r
- UINT16 Dfes:1; // Device Fatal Error Status\r
-\r
- UINT16 Utpes:1; // UTP Error Status\r
- UINT16 Rsvd1:3;\r
-\r
- UINT16 Hcfes:1; // Host Controller Fatal Error Status\r
- UINT16 Sbfes:1; // System Bus Fatal Error Status\r
- UINT16 Rsvd2:14;\r
+ UINT16 Utrcs : 1; // UTP Transfer Request Completion Status\r
+ UINT16 Udepri : 1; // UIC DME_ENDPOINT_RESET Indication\r
+ UINT16 Ue : 1; // UIC Error\r
+ UINT16 Utms : 1; // UIC Test Mode Status\r
+\r
+ UINT16 Upms : 1; // UIC Power Mode Status\r
+ UINT16 Uhxs : 1; // UIC Hibernate Exit Status\r
+ UINT16 Uhes : 1; // UIC Hibernate Enter Status\r
+ UINT16 Ulls : 1; // UIC Link Lost Status\r
+\r
+ UINT16 Ulss : 1; // UIC Link Startup Status\r
+ UINT16 Utmrcs : 1; // UTP Task Management Request Completion Status\r
+ UINT16 Uccs : 1; // UIC Command Completion Status\r
+ UINT16 Dfes : 1; // Device Fatal Error Status\r
+\r
+ UINT16 Utpes : 1; // UTP Error Status\r
+ UINT16 Rsvd1 : 3;\r
+\r
+ UINT16 Hcfes : 1; // Host Controller Fatal Error Status\r
+ UINT16 Sbfes : 1; // System Bus Fatal Error Status\r
+ UINT16 Rsvd2 : 14;\r
} UFS_HC_IS;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.2 Offset 24h: IE - Interrupt Enable\r
//\r
typedef struct {\r
- UINT16 Utrce:1; // UTP Transfer Request Completion Enable\r
- UINT16 Udeprie:1; // UIC DME_ENDPOINT_RESET Enable\r
- UINT16 Uee:1; // UIC Error Enable\r
- UINT16 Utmse:1; // UIC Test Mode Status Enable\r
-\r
- UINT16 Upmse:1; // UIC Power Mode Status Enable\r
- UINT16 Uhxse:1; // UIC Hibernate Exit Status Enable\r
- UINT16 Uhese:1; // UIC Hibernate Enter Status Enable\r
- UINT16 Ullse:1; // UIC Link Lost Status Enable\r
-\r
- UINT16 Ulsse:1; // UIC Link Startup Status Enable\r
- UINT16 Utmrce:1; // UTP Task Management Request Completion Enable\r
- UINT16 Ucce:1; // UIC Command Completion Enable\r
- UINT16 Dfee:1; // Device Fatal Error Enable\r
-\r
- UINT16 Utpee:1; // UTP Error Enable\r
- UINT16 Rsvd1:3;\r
-\r
- UINT16 Hcfee:1; // Host Controller Fatal Error Enable\r
- UINT16 Sbfee:1; // System Bus Fatal Error Enable\r
- UINT16 Rsvd2:14;\r
+ UINT16 Utrce : 1; // UTP Transfer Request Completion Enable\r
+ UINT16 Udeprie : 1; // UIC DME_ENDPOINT_RESET Enable\r
+ UINT16 Uee : 1; // UIC Error Enable\r
+ UINT16 Utmse : 1; // UIC Test Mode Status Enable\r
+\r
+ UINT16 Upmse : 1; // UIC Power Mode Status Enable\r
+ UINT16 Uhxse : 1; // UIC Hibernate Exit Status Enable\r
+ UINT16 Uhese : 1; // UIC Hibernate Enter Status Enable\r
+ UINT16 Ullse : 1; // UIC Link Lost Status Enable\r
+\r
+ UINT16 Ulsse : 1; // UIC Link Startup Status Enable\r
+ UINT16 Utmrce : 1; // UTP Task Management Request Completion Enable\r
+ UINT16 Ucce : 1; // UIC Command Completion Enable\r
+ UINT16 Dfee : 1; // Device Fatal Error Enable\r
+\r
+ UINT16 Utpee : 1; // UTP Error Enable\r
+ UINT16 Rsvd1 : 3;\r
+\r
+ UINT16 Hcfee : 1; // Host Controller Fatal Error Enable\r
+ UINT16 Sbfee : 1; // System Bus Fatal Error Enable\r
+ UINT16 Rsvd2 : 14;\r
} UFS_HC_IE;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.3 Offset 30h: HCS - Host Controller Status\r
//\r
typedef struct {\r
- UINT8 Dp:1; // Device Present\r
- UINT8 UtrlRdy:1; // UTP Transfer Request List Ready\r
- UINT8 UtmrlRdy:1; // UTP Task Management Request List Ready\r
- UINT8 UcRdy:1; // UIC COMMAND Ready\r
- UINT8 Rsvd1:4;\r
-\r
- UINT8 Upmcrs:3; // UIC Power Mode Change Request Status\r
- UINT8 Rsvd2:1; // UIC Hibernate Exit Status Enable\r
- UINT8 Utpec:4; // UTP Error Code\r
-\r
- UINT8 TtagUtpE; // Task Tag of UTP error\r
- UINT8 TlunUtpE; // Target LUN of UTP error\r
+ UINT8 Dp : 1; // Device Present\r
+ UINT8 UtrlRdy : 1; // UTP Transfer Request List Ready\r
+ UINT8 UtmrlRdy : 1; // UTP Task Management Request List Ready\r
+ UINT8 UcRdy : 1; // UIC COMMAND Ready\r
+ UINT8 Rsvd1 : 4;\r
+\r
+ UINT8 Upmcrs : 3; // UIC Power Mode Change Request Status\r
+ UINT8 Rsvd2 : 1; // UIC Hibernate Exit Status Enable\r
+ UINT8 Utpec : 4; // UTP Error Code\r
+\r
+ UINT8 TtagUtpE; // Task Tag of UTP error\r
+ UINT8 TlunUtpE; // Target LUN of UTP error\r
} UFS_HC_STATUS;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.4 Offset 34h: HCE - Host Controller Enable\r
//\r
typedef struct {\r
- UINT32 Hce:1; // Host Controller Enable\r
- UINT32 Rsvd1:31;\r
+ UINT32 Hce : 1; // Host Controller Enable\r
+ UINT32 Rsvd1 : 31;\r
} UFS_HC_ENABLE;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.5 Offset 38h: UECPA - Host UIC Error Code PHY Adapter Layer\r
//\r
typedef struct {\r
- UINT32 Ec:5; // UIC PHY Adapter Layer Error Code\r
- UINT32 Rsvd1:26;\r
- UINT32 Err:1; // UIC PHY Adapter Layer Error\r
+ UINT32 Ec : 5; // UIC PHY Adapter Layer Error Code\r
+ UINT32 Rsvd1 : 26;\r
+ UINT32 Err : 1; // UIC PHY Adapter Layer Error\r
} UFS_HC_UECPA;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.6 Offset 3ch: UECDL - Host UIC Error Code Data Link Layer\r
//\r
typedef struct {\r
- UINT32 Ec:15; // UIC Data Link Layer Error Code\r
- UINT32 Rsvd1:16;\r
- UINT32 Err:1; // UIC Data Link Layer Error\r
+ UINT32 Ec : 15; // UIC Data Link Layer Error Code\r
+ UINT32 Rsvd1 : 16;\r
+ UINT32 Err : 1; // UIC Data Link Layer Error\r
} UFS_HC_UECDL;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.7 Offset 40h: UECN - Host UIC Error Code Network Layer\r
//\r
typedef struct {\r
- UINT32 Ec:3; // UIC Network Layer Error Code\r
- UINT32 Rsvd1:28;\r
- UINT32 Err:1; // UIC Network Layer Error\r
+ UINT32 Ec : 3; // UIC Network Layer Error Code\r
+ UINT32 Rsvd1 : 28;\r
+ UINT32 Err : 1; // UIC Network Layer Error\r
} UFS_HC_UECN;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.8 Offset 44h: UECT - Host UIC Error Code Transport Layer\r
//\r
typedef struct {\r
- UINT32 Ec:7; // UIC Transport Layer Error Code\r
- UINT32 Rsvd1:24;\r
- UINT32 Err:1; // UIC Transport Layer Error\r
+ UINT32 Ec : 7; // UIC Transport Layer Error Code\r
+ UINT32 Rsvd1 : 24;\r
+ UINT32 Err : 1; // UIC Transport Layer Error\r
} UFS_HC_UECT;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.9 Offset 48h: UECDME - Host UIC Error Code\r
//\r
typedef struct {\r
- UINT32 Ec:1; // UIC DME Error Code\r
- UINT32 Rsvd1:30;\r
- UINT32 Err:1; // UIC DME Error\r
+ UINT32 Ec : 1; // UIC DME Error Code\r
+ UINT32 Rsvd1 : 30;\r
+ UINT32 Err : 1; // UIC DME Error\r
} UFS_HC_UECDME;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.3.10 Offset 4Ch: UTRIACR - UTP Transfer Request Interrupt Aggregation Control Register\r
//\r
typedef struct {\r
- UINT8 IaToVal; // Interrupt aggregation timeout value\r
+ UINT8 IaToVal; // Interrupt aggregation timeout value\r
\r
- UINT8 IacTh:5; // Interrupt aggregation counter threshold\r
- UINT8 Rsvd1:3;\r
+ UINT8 IacTh : 5; // Interrupt aggregation counter threshold\r
+ UINT8 Rsvd1 : 3;\r
\r
- UINT8 Ctr:1; // Counter and Timer Reset\r
- UINT8 Rsvd2:3;\r
- UINT8 Iasb:1; // Interrupt aggregation status bit\r
- UINT8 Rsvd3:3;\r
+ UINT8 Ctr : 1; // Counter and Timer Reset\r
+ UINT8 Rsvd2 : 3;\r
+ UINT8 Iasb : 1; // Interrupt aggregation status bit\r
+ UINT8 Rsvd3 : 3;\r
\r
- UINT8 IapwEn:1; // Interrupt aggregation parameter write enable\r
- UINT8 Rsvd4:6;\r
- UINT8 IaEn:1; // Interrupt Aggregation Enable/Disable\r
+ UINT8 IapwEn : 1; // Interrupt aggregation parameter write enable\r
+ UINT8 Rsvd4 : 6;\r
+ UINT8 IaEn : 1; // Interrupt Aggregation Enable/Disable\r
} UFS_HC_UTRIACR;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.4.1 Offset 50h: UTRLBA - UTP Transfer Request List Base Address\r
//\r
typedef struct {\r
- UINT32 Rsvd1:10;\r
- UINT32 UtrlBa:22; // UTP Transfer Request List Base Address\r
+ UINT32 Rsvd1 : 10;\r
+ UINT32 UtrlBa : 22; // UTP Transfer Request List Base Address\r
} UFS_HC_UTRLBA;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.4.2 Offset 54h: UTRLBAU - UTP Transfer Request List Base Address Upper 32-bits\r
//\r
-#define UFS_HC_UTRLBAU UINT32\r
+#define UFS_HC_UTRLBAU UINT32\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.4.3 Offset 58h: UTRLDBR - UTP Transfer Request List Door Bell Register\r
//\r
-#define UFS_HC_UTRLDBR UINT32\r
+#define UFS_HC_UTRLDBR UINT32\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.4.4 Offset 5Ch: UTRLCLR - UTP Transfer Request List CLear Register\r
//\r
-#define UFS_HC_UTRLCLR UINT32\r
+#define UFS_HC_UTRLCLR UINT32\r
\r
#if 0\r
//\r
// UFSHCI 2.0 Spec Section 5.4.5 Offset 60h: UTRLRSR - UTP Transfer Request List Run Stop Register\r
//\r
typedef struct {\r
- UINT32 UtrlRsr:1; // UTP Transfer Request List Run-Stop Register\r
- UINT32 Rsvd1:31;\r
+ UINT32 UtrlRsr : 1; // UTP Transfer Request List Run-Stop Register\r
+ UINT32 Rsvd1 : 31;\r
} UFS_HC_UTRLRSR;\r
#endif\r
\r
// UFSHCI 2.0 Spec Section 5.5.1 Offset 70h: UTMRLBA - UTP Task Management Request List Base Address\r
//\r
typedef struct {\r
- UINT32 Rsvd1:10;\r
- UINT32 UtmrlBa:22; // UTP Task Management Request List Base Address\r
+ UINT32 Rsvd1 : 10;\r
+ UINT32 UtmrlBa : 22; // UTP Task Management Request List Base Address\r
} UFS_HC_UTMRLBA;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.5.2 Offset 74h: UTMRLBAU - UTP Task Management Request List Base Address Upper 32-bits\r
//\r
-#define UFS_HC_UTMRLBAU UINT32\r
+#define UFS_HC_UTMRLBAU UINT32\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.5.3 Offset 78h: UTMRLDBR - UTP Task Management Request List Door Bell Register\r
//\r
typedef struct {\r
- UINT32 UtmrlDbr:8; // UTP Task Management Request List Door bell Register\r
- UINT32 Rsvd1:24;\r
+ UINT32 UtmrlDbr : 8; // UTP Task Management Request List Door bell Register\r
+ UINT32 Rsvd1 : 24;\r
} UFS_HC_UTMRLDBR;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.5.4 Offset 7Ch: UTMRLCLR - UTP Task Management Request List CLear Register\r
//\r
typedef struct {\r
- UINT32 UtmrlClr:8; // UTP Task Management List Clear Register\r
- UINT32 Rsvd1:24;\r
+ UINT32 UtmrlClr : 8; // UTP Task Management List Clear Register\r
+ UINT32 Rsvd1 : 24;\r
} UFS_HC_UTMRLCLR;\r
\r
#if 0\r
// UFSHCI 2.0 Spec Section 5.5.5 Offset 80h: UTMRLRSR - UTP Task Management Request List Run Stop Register\r
//\r
typedef struct {\r
- UINT32 UtmrlRsr:1; // UTP Task Management Request List Run-Stop Register\r
- UINT32 Rsvd1:31;\r
+ UINT32 UtmrlRsr : 1; // UTP Task Management Request List Run-Stop Register\r
+ UINT32 Rsvd1 : 31;\r
} UFS_HC_UTMRLRSR;\r
#endif\r
\r
// UFSHCI 2.0 Spec Section 5.6.1 Offset 90h: UICCMD - UIC Command\r
//\r
typedef struct {\r
- UINT32 CmdOp:8; // Command Opcode\r
- UINT32 Rsvd1:24;\r
+ UINT32 CmdOp : 8; // Command Opcode\r
+ UINT32 Rsvd1 : 24;\r
} UFS_HC_UICCMD;\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.6.2 Offset 94h: UICCMDARG1 - UIC Command Argument 1\r
//\r
-#define UFS_HC_UICCMD_ARG1 UINT32\r
+#define UFS_HC_UICCMD_ARG1 UINT32\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.6.2 Offset 98h: UICCMDARG2 - UIC Command Argument 2\r
//\r
-#define UFS_HC_UICCMD_ARG2 UINT32\r
+#define UFS_HC_UICCMD_ARG2 UINT32\r
\r
//\r
// UFSHCI 2.0 Spec Section 5.6.2 Offset 9ch: UICCMDARG3 - UIC Command Argument 3\r
//\r
-#define UFS_HC_UICCMD_ARG3 UINT32\r
+#define UFS_HC_UICCMD_ARG3 UINT32\r
\r
//\r
// UIC command opcodes\r
//\r
// DW0\r
//\r
- UINT32 Rsvd1:24;\r
- UINT32 Int:1; /* Interrupt */\r
- UINT32 Dd:2; /* Data Direction */\r
- UINT32 Rsvd2:1;\r
- UINT32 Ct:4; /* Command Type */\r
+ UINT32 Rsvd1 : 24;\r
+ UINT32 Int : 1; /* Interrupt */\r
+ UINT32 Dd : 2; /* Data Direction */\r
+ UINT32 Rsvd2 : 1;\r
+ UINT32 Ct : 4; /* Command Type */\r
\r
//\r
// DW1\r
//\r
- UINT32 Rsvd3;\r
+ UINT32 Rsvd3;\r
\r
//\r
// DW2\r
//\r
- UINT32 Ocs:8; /* Overall Command Status */\r
- UINT32 Rsvd4:24;\r
+ UINT32 Ocs : 8; /* Overall Command Status */\r
+ UINT32 Rsvd4 : 24;\r
\r
//\r
// DW3\r
//\r
- UINT32 Rsvd5;\r
+ UINT32 Rsvd5;\r
\r
//\r
// DW4\r
//\r
- UINT32 Rsvd6:7;\r
- UINT32 UcdBa:25; /* UTP Command Descriptor Base Address */\r
+ UINT32 Rsvd6 : 7;\r
+ UINT32 UcdBa : 25; /* UTP Command Descriptor Base Address */\r
\r
//\r
// DW5\r
//\r
- UINT32 UcdBaU; /* UTP Command Descriptor Base Address Upper 32-bits */\r
+ UINT32 UcdBaU; /* UTP Command Descriptor Base Address Upper 32-bits */\r
\r
//\r
// DW6\r
//\r
- UINT16 RuL; /* Response UPIU Length */\r
- UINT16 RuO; /* Response UPIU Offset */\r
+ UINT16 RuL; /* Response UPIU Length */\r
+ UINT16 RuO; /* Response UPIU Offset */\r
\r
//\r
// DW7\r
//\r
- UINT16 PrdtL; /* PRDT Length */\r
- UINT16 PrdtO; /* PRDT Offset */\r
+ UINT16 PrdtL; /* PRDT Length */\r
+ UINT16 PrdtO; /* PRDT Offset */\r
} UTP_TRD;\r
\r
typedef struct {\r
//\r
// DW0\r
//\r
- UINT32 Rsvd1:2;\r
- UINT32 DbAddr:30; /* Data Base Address */\r
+ UINT32 Rsvd1 : 2;\r
+ UINT32 DbAddr : 30; /* Data Base Address */\r
\r
//\r
// DW1\r
//\r
- UINT32 DbAddrU; /* Data Base Address Upper 32-bits */\r
+ UINT32 DbAddrU; /* Data Base Address Upper 32-bits */\r
\r
//\r
// DW2\r
//\r
- UINT32 Rsvd2;\r
+ UINT32 Rsvd2;\r
\r
//\r
// DW3\r
//\r
- UINT32 DbCount:18; /* Data Byte Count */\r
- UINT32 Rsvd3:14;\r
+ UINT32 DbCount : 18; /* Data Byte Count */\r
+ UINT32 Rsvd3 : 14;\r
} UTP_TR_PRD;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x01*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x01*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 CmdSet:4; /* Command Set Type */\r
- UINT8 Rsvd1:4;\r
- UINT8 Rsvd2;\r
- UINT8 Rsvd3;\r
- UINT8 Rsvd4;\r
+ UINT8 CmdSet : 4; /* Command Set Type */\r
+ UINT8 Rsvd1 : 4;\r
+ UINT8 Rsvd2;\r
+ UINT8 Rsvd3;\r
+ UINT8 Rsvd4;\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd5;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd5;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
\r
//\r
// DW3\r
//\r
- UINT32 ExpDataTranLen; /* Expected Data Transfer Length - Big Endian */\r
+ UINT32 ExpDataTranLen; /* Expected Data Transfer Length - Big Endian */\r
\r
//\r
// DW4 - DW7\r
//\r
- UINT8 Cdb[16];\r
+ UINT8 Cdb[16];\r
} UTP_COMMAND_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x21*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x21*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 CmdSet:4; /* Command Set Type */\r
- UINT8 Rsvd1:4;\r
- UINT8 Rsvd2;\r
- UINT8 Response; /* Response */\r
- UINT8 Status; /* Status */\r
+ UINT8 CmdSet : 4; /* Command Set Type */\r
+ UINT8 Rsvd1 : 4;\r
+ UINT8 Rsvd2;\r
+ UINT8 Response; /* Response */\r
+ UINT8 Status; /* Status */\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 DevInfo; /* Device Information */\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 DevInfo; /* Device Information */\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
\r
//\r
// DW3\r
//\r
- UINT32 ResTranCount; /* Residual Transfer Count - Big Endian */\r
+ UINT32 ResTranCount; /* Residual Transfer Count - Big Endian */\r
\r
//\r
// DW4 - DW7\r
//\r
- UINT8 Rsvd3[16];\r
+ UINT8 Rsvd3[16];\r
\r
//\r
// Data Segment - Sense Data\r
//\r
- UINT16 SenseDataLen; /* Sense Data Length - Big Endian */\r
- UINT8 SenseData[18]; /* Sense Data */\r
+ UINT16 SenseDataLen; /* Sense Data Length - Big Endian */\r
+ UINT8 SenseData[18]; /* Sense Data */\r
} UTP_RESPONSE_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x02*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x02*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd1[4];\r
+ UINT8 Rsvd1[4];\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd2;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd2;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
\r
//\r
// DW3\r
//\r
- UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
+ UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
\r
//\r
// DW4\r
//\r
- UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
+ UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
\r
//\r
// DW5 - DW7\r
//\r
- UINT8 Rsvd3[12];\r
+ UINT8 Rsvd3[12];\r
\r
//\r
// Data Segment - Data to be sent out\r
//\r
- //UINT8 Data[]; /* Data to be sent out, maximum is 65535 bytes */\r
+ // UINT8 Data[]; /* Data to be sent out, maximum is 65535 bytes */\r
} UTP_DATA_OUT_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x22*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x22*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd1[4];\r
+ UINT8 Rsvd1[4];\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd2;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd2;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
\r
//\r
// DW3\r
//\r
- UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
+ UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
\r
//\r
// DW4\r
//\r
- UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
+ UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
\r
//\r
// DW5 - DW7\r
//\r
- UINT8 Rsvd3[12];\r
+ UINT8 Rsvd3[12];\r
\r
//\r
// Data Segment - Data to be read\r
//\r
- //UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */\r
+ // UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */\r
} UTP_DATA_IN_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x31*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x31*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd1[4];\r
+ UINT8 Rsvd1[4];\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd2;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd2;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
\r
//\r
// DW3\r
//\r
- UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
+ UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
\r
//\r
// DW4\r
//\r
- UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
+ UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
\r
//\r
// DW5 - DW7\r
//\r
- UINT8 Rsvd3[12];\r
+ UINT8 Rsvd3[12];\r
\r
//\r
// Data Segment - Data to be read\r
//\r
- //UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */\r
+ // UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */\r
} UTP_RDY_TO_TRAN_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x04*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x04*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd1;\r
- UINT8 TskManFunc; /* Task Management Function */\r
- UINT8 Rsvd2[2];\r
+ UINT8 Rsvd1;\r
+ UINT8 TskManFunc; /* Task Management Function */\r
+ UINT8 Rsvd2[2];\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd3;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd3;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
\r
//\r
// DW3\r
//\r
- UINT32 InputParam1; /* Input Parameter 1 - Big Endian */\r
+ UINT32 InputParam1; /* Input Parameter 1 - Big Endian */\r
\r
//\r
// DW4\r
//\r
- UINT32 InputParam2; /* Input Parameter 2 - Big Endian */\r
+ UINT32 InputParam2; /* Input Parameter 2 - Big Endian */\r
\r
//\r
// DW5\r
//\r
- UINT32 InputParam3; /* Input Parameter 3 - Big Endian */\r
+ UINT32 InputParam3; /* Input Parameter 3 - Big Endian */\r
\r
//\r
// DW6 - DW7\r
//\r
- UINT8 Rsvd4[8];\r
+ UINT8 Rsvd4[8];\r
} UTP_TM_REQ_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x24*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x24*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd1[2];\r
- UINT8 Resp; /* Response */\r
- UINT8 Rsvd2;\r
+ UINT8 Rsvd1[2];\r
+ UINT8 Resp; /* Response */\r
+ UINT8 Rsvd2;\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd3;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd3;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
\r
//\r
// DW3\r
//\r
- UINT32 OutputParam1; /* Output Parameter 1 - Big Endian */\r
+ UINT32 OutputParam1; /* Output Parameter 1 - Big Endian */\r
\r
//\r
// DW4\r
//\r
- UINT32 OutputParam2; /* Output Parameter 2 - Big Endian */\r
+ UINT32 OutputParam2; /* Output Parameter 2 - Big Endian */\r
\r
//\r
// DW5 - DW7\r
//\r
- UINT8 Rsvd4[12];\r
+ UINT8 Rsvd4[12];\r
} UTP_TM_RESP_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT32 Rsvd1:24;\r
- UINT32 Int:1; /* Interrupt */\r
- UINT32 Rsvd2:7;\r
+ UINT32 Rsvd1 : 24;\r
+ UINT32 Int : 1; /* Interrupt */\r
+ UINT32 Rsvd2 : 7;\r
\r
//\r
// DW1\r
//\r
- UINT32 Rsvd3;\r
+ UINT32 Rsvd3;\r
\r
//\r
// DW2\r
//\r
- UINT32 Ocs:8; /* Overall Command Status */\r
- UINT32 Rsvd4:24;\r
+ UINT32 Ocs : 8; /* Overall Command Status */\r
+ UINT32 Rsvd4 : 24;\r
\r
//\r
// DW3\r
//\r
- UINT32 Rsvd5;\r
+ UINT32 Rsvd5;\r
\r
//\r
// DW4 - DW11\r
//\r
- UTP_TM_REQ_UPIU TmReq; /* Task Management Request UPIU */\r
+ UTP_TM_REQ_UPIU TmReq; /* Task Management Request UPIU */\r
\r
//\r
// DW12 - DW19\r
//\r
- UTP_TM_RESP_UPIU TmResp; /* Task Management Response UPIU */\r
+ UTP_TM_RESP_UPIU TmResp; /* Task Management Response UPIU */\r
} UTP_TMRD;\r
\r
-\r
typedef struct {\r
- UINT8 Opcode;\r
- UINT8 DescId;\r
- UINT8 Index;\r
- UINT8 Selector;\r
- UINT16 Rsvd1;\r
- UINT16 Length;\r
- UINT32 Value;\r
- UINT32 Rsvd2;\r
+ UINT8 Opcode;\r
+ UINT8 DescId;\r
+ UINT8 Index;\r
+ UINT8 Selector;\r
+ UINT16 Rsvd1;\r
+ UINT16 Length;\r
+ UINT32 Value;\r
+ UINT32 Rsvd2;\r
} UTP_UPIU_TSF;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x16*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Rsvd1;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x16*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Rsvd1;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd2;\r
- UINT8 QueryFunc; /* Query Function */\r
- UINT8 Rsvd3[2];\r
+ UINT8 Rsvd2;\r
+ UINT8 QueryFunc; /* Query Function */\r
+ UINT8 Rsvd3[2];\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd4;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd4;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
\r
//\r
// DW3 - 6\r
//\r
- UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */\r
+ UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */\r
\r
//\r
// DW7\r
//\r
- UINT8 Rsvd5[4];\r
+ UINT8 Rsvd5[4];\r
\r
//\r
// Data Segment - Data to be transferred\r
//\r
- //UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */\r
+ // UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */\r
} UTP_QUERY_REQ_UPIU;\r
\r
-#define QUERY_FUNC_STD_READ_REQ 0x01\r
-#define QUERY_FUNC_STD_WRITE_REQ 0x81\r
+#define QUERY_FUNC_STD_READ_REQ 0x01\r
+#define QUERY_FUNC_STD_WRITE_REQ 0x81\r
\r
typedef enum {\r
- UtpQueryFuncOpcodeNop = 0x00,\r
- UtpQueryFuncOpcodeRdDesc = 0x01,\r
- UtpQueryFuncOpcodeWrDesc = 0x02,\r
- UtpQueryFuncOpcodeRdAttr = 0x03,\r
- UtpQueryFuncOpcodeWrAttr = 0x04,\r
- UtpQueryFuncOpcodeRdFlag = 0x05,\r
- UtpQueryFuncOpcodeSetFlag = 0x06,\r
- UtpQueryFuncOpcodeClrFlag = 0x07,\r
- UtpQueryFuncOpcodeTogFlag = 0x08\r
+ UtpQueryFuncOpcodeNop = 0x00,\r
+ UtpQueryFuncOpcodeRdDesc = 0x01,\r
+ UtpQueryFuncOpcodeWrDesc = 0x02,\r
+ UtpQueryFuncOpcodeRdAttr = 0x03,\r
+ UtpQueryFuncOpcodeWrAttr = 0x04,\r
+ UtpQueryFuncOpcodeRdFlag = 0x05,\r
+ UtpQueryFuncOpcodeSetFlag = 0x06,\r
+ UtpQueryFuncOpcodeClrFlag = 0x07,\r
+ UtpQueryFuncOpcodeTogFlag = 0x08\r
} UTP_QUERY_FUNC_OPCODE;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x36*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Rsvd1;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x36*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Rsvd1;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd2;\r
- UINT8 QueryFunc; /* Query Function */\r
- UINT8 QueryResp; /* Query Response */\r
- UINT8 Rsvd3;\r
+ UINT8 Rsvd2;\r
+ UINT8 QueryFunc; /* Query Function */\r
+ UINT8 QueryResp; /* Query Response */\r
+ UINT8 Rsvd3;\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 DevInfo; /* Device Information */\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 DevInfo; /* Device Information */\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
\r
//\r
// DW3 - 6\r
//\r
- UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */\r
+ UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */\r
\r
//\r
// DW7\r
//\r
- UINT8 Rsvd4[4];\r
+ UINT8 Rsvd4[4];\r
\r
//\r
// Data Segment - Data to be transferred\r
//\r
- //UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */\r
+ // UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */\r
} UTP_QUERY_RESP_UPIU;\r
\r
typedef enum {\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x3F*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Lun;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x3F*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Lun;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd1[2];\r
- UINT8 Response; /* Response - 0x01 */\r
- UINT8 Rsvd2;\r
+ UINT8 Rsvd1[2];\r
+ UINT8 Response; /* Response - 0x01 */\r
+ UINT8 Rsvd2;\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 DevInfo; /* Device Information - 0x00 */\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 DevInfo; /* Device Information - 0x00 */\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
\r
//\r
// DW3\r
//\r
- UINT8 HdrSts; /* Basic Header Status */\r
- UINT8 Rsvd3;\r
- UINT8 E2ESts; /* End-to-End Status */\r
- UINT8 Rsvd4;\r
+ UINT8 HdrSts; /* Basic Header Status */\r
+ UINT8 Rsvd3;\r
+ UINT8 E2ESts; /* End-to-End Status */\r
+ UINT8 Rsvd4;\r
\r
//\r
// DW4 - DW7\r
//\r
- UINT8 Rsvd5[16];\r
+ UINT8 Rsvd5[16];\r
} UTP_REJ_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x00*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Rsvd1;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x00*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Rsvd1;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd2[4];\r
+ UINT8 Rsvd2[4];\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 Rsvd3;\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 Rsvd3;\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
\r
//\r
// DW3 - DW7\r
//\r
- UINT8 Rsvd4[20];\r
+ UINT8 Rsvd4[20];\r
} UTP_NOP_OUT_UPIU;\r
\r
//\r
//\r
// DW0\r
//\r
- UINT8 TransCode:6; /* Transaction Type - 0x20*/\r
- UINT8 Dd:1;\r
- UINT8 Hd:1;\r
- UINT8 Flags;\r
- UINT8 Rsvd1;\r
- UINT8 TaskTag; /* Task Tag */\r
+ UINT8 TransCode : 6; /* Transaction Type - 0x20*/\r
+ UINT8 Dd : 1;\r
+ UINT8 Hd : 1;\r
+ UINT8 Flags;\r
+ UINT8 Rsvd1;\r
+ UINT8 TaskTag; /* Task Tag */\r
\r
//\r
// DW1\r
//\r
- UINT8 Rsvd2[2];\r
- UINT8 Resp; /* Response - 0x00 */\r
- UINT8 Rsvd3;\r
+ UINT8 Rsvd2[2];\r
+ UINT8 Resp; /* Response - 0x00 */\r
+ UINT8 Rsvd3;\r
\r
//\r
// DW2\r
//\r
- UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
- UINT8 DevInfo; /* Device Information - 0x00 */\r
- UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
+ UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
+ UINT8 DevInfo; /* Device Information - 0x00 */\r
+ UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
\r
//\r
// DW3 - DW7\r
//\r
- UINT8 Rsvd4[20];\r
+ UINT8 Rsvd4[20];\r
} UTP_NOP_IN_UPIU;\r
\r
//\r
// UFS Descriptors\r
//\r
typedef enum {\r
- UfsDeviceDesc = 0x00,\r
- UfsConfigDesc = 0x01,\r
- UfsUnitDesc = 0x02,\r
- UfsInterConnDesc = 0x04,\r
- UfsStringDesc = 0x05,\r
- UfsGeometryDesc = 0x07,\r
- UfsPowerDesc = 0x08\r
+ UfsDeviceDesc = 0x00,\r
+ UfsConfigDesc = 0x01,\r
+ UfsUnitDesc = 0x02,\r
+ UfsInterConnDesc = 0x04,\r
+ UfsStringDesc = 0x05,\r
+ UfsGeometryDesc = 0x07,\r
+ UfsPowerDesc = 0x08\r
} UFS_DESC_IDN;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.2 - Device Descriptor\r
//\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- UINT8 Device;\r
- UINT8 DevClass;\r
- UINT8 DevSubClass;\r
- UINT8 Protocol;\r
- UINT8 NumLun;\r
- UINT8 NumWLun;\r
- UINT8 BootEn;\r
- UINT8 DescAccessEn;\r
- UINT8 InitPowerMode;\r
- UINT8 HighPriorityLun;\r
- UINT8 SecureRemovalType;\r
- UINT8 SecurityLun;\r
- UINT8 BgOpsTermLat;\r
- UINT8 InitActiveIccLevel;\r
- UINT16 SpecVersion;\r
- UINT16 ManufactureDate;\r
- UINT8 ManufacturerName;\r
- UINT8 ProductName;\r
- UINT8 SerialName;\r
- UINT8 OemId;\r
- UINT16 ManufacturerId;\r
- UINT8 Ud0BaseOffset;\r
- UINT8 Ud0ConfParamLen;\r
- UINT8 DevRttCap;\r
- UINT16 PeriodicRtcUpdate;\r
- UINT8 Rsvd1[17];\r
- UINT8 Rsvd2[16];\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ UINT8 Device;\r
+ UINT8 DevClass;\r
+ UINT8 DevSubClass;\r
+ UINT8 Protocol;\r
+ UINT8 NumLun;\r
+ UINT8 NumWLun;\r
+ UINT8 BootEn;\r
+ UINT8 DescAccessEn;\r
+ UINT8 InitPowerMode;\r
+ UINT8 HighPriorityLun;\r
+ UINT8 SecureRemovalType;\r
+ UINT8 SecurityLun;\r
+ UINT8 BgOpsTermLat;\r
+ UINT8 InitActiveIccLevel;\r
+ UINT16 SpecVersion;\r
+ UINT16 ManufactureDate;\r
+ UINT8 ManufacturerName;\r
+ UINT8 ProductName;\r
+ UINT8 SerialName;\r
+ UINT8 OemId;\r
+ UINT16 ManufacturerId;\r
+ UINT8 Ud0BaseOffset;\r
+ UINT8 Ud0ConfParamLen;\r
+ UINT8 DevRttCap;\r
+ UINT16 PeriodicRtcUpdate;\r
+ UINT8 Rsvd1[17];\r
+ UINT8 Rsvd2[16];\r
} UFS_DEV_DESC;\r
\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- UINT8 Rsvd1;\r
- UINT8 BootEn;\r
- UINT8 DescAccessEn;\r
- UINT8 InitPowerMode;\r
- UINT8 HighPriorityLun;\r
- UINT8 SecureRemovalType;\r
- UINT8 InitActiveIccLevel;\r
- UINT16 PeriodicRtcUpdate;\r
- UINT8 Rsvd2[5];\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ UINT8 Rsvd1;\r
+ UINT8 BootEn;\r
+ UINT8 DescAccessEn;\r
+ UINT8 InitPowerMode;\r
+ UINT8 HighPriorityLun;\r
+ UINT8 SecureRemovalType;\r
+ UINT8 InitActiveIccLevel;\r
+ UINT16 PeriodicRtcUpdate;\r
+ UINT8 Rsvd2[5];\r
} UFS_CONFIG_DESC_GEN_HEADER;\r
\r
typedef struct {\r
- UINT8 LunEn;\r
- UINT8 BootLunId;\r
- UINT8 LunWriteProt;\r
- UINT8 MemType;\r
- UINT32 NumAllocUnits;\r
- UINT8 DataReliability;\r
- UINT8 LogicBlkSize;\r
- UINT8 ProvisionType;\r
- UINT16 CtxCap;\r
- UINT8 Rsvd1[3];\r
+ UINT8 LunEn;\r
+ UINT8 BootLunId;\r
+ UINT8 LunWriteProt;\r
+ UINT8 MemType;\r
+ UINT32 NumAllocUnits;\r
+ UINT8 DataReliability;\r
+ UINT8 LogicBlkSize;\r
+ UINT8 ProvisionType;\r
+ UINT16 CtxCap;\r
+ UINT8 Rsvd1[3];\r
} UFS_UNIT_DESC_CONFIG_PARAMS;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.3 - Configuration Descriptor\r
//\r
typedef struct {\r
- UFS_CONFIG_DESC_GEN_HEADER Header;\r
- UFS_UNIT_DESC_CONFIG_PARAMS UnitDescConfParams[8];\r
+ UFS_CONFIG_DESC_GEN_HEADER Header;\r
+ UFS_UNIT_DESC_CONFIG_PARAMS UnitDescConfParams[8];\r
} UFS_CONFIG_DESC;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.4 - Geometry Descriptor\r
//\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- UINT8 MediaTech;\r
- UINT8 Rsvd1;\r
- UINT64 TotalRawDevCapacity;\r
- UINT8 Rsvd2;\r
- UINT32 SegSize;\r
- UINT8 AllocUnitSize;\r
- UINT8 MinAddrBlkSize;\r
- UINT8 OptReadBlkSize;\r
- UINT8 OptWriteBlkSize;\r
- UINT8 MaxInBufSize;\r
- UINT8 MaxOutBufSize;\r
- UINT8 RpmbRwSize;\r
- UINT8 Rsvd3;\r
- UINT8 DataOrder;\r
- UINT8 MaxCtxIdNum;\r
- UINT8 SysDataTagUnitSize;\r
- UINT8 SysDataResUnitSize;\r
- UINT8 SupSecRemovalTypes;\r
- UINT16 SupMemTypes;\r
- UINT32 SysCodeMaxNumAllocUnits;\r
- UINT16 SupCodeCapAdjFac;\r
- UINT32 NonPersMaxNumAllocUnits;\r
- UINT16 NonPersCapAdjFac;\r
- UINT32 Enhance1MaxNumAllocUnits;\r
- UINT16 Enhance1CapAdjFac;\r
- UINT32 Enhance2MaxNumAllocUnits;\r
- UINT16 Enhance2CapAdjFac;\r
- UINT32 Enhance3MaxNumAllocUnits;\r
- UINT16 Enhance3CapAdjFac;\r
- UINT32 Enhance4MaxNumAllocUnits;\r
- UINT16 Enhance4CapAdjFac;\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ UINT8 MediaTech;\r
+ UINT8 Rsvd1;\r
+ UINT64 TotalRawDevCapacity;\r
+ UINT8 Rsvd2;\r
+ UINT32 SegSize;\r
+ UINT8 AllocUnitSize;\r
+ UINT8 MinAddrBlkSize;\r
+ UINT8 OptReadBlkSize;\r
+ UINT8 OptWriteBlkSize;\r
+ UINT8 MaxInBufSize;\r
+ UINT8 MaxOutBufSize;\r
+ UINT8 RpmbRwSize;\r
+ UINT8 Rsvd3;\r
+ UINT8 DataOrder;\r
+ UINT8 MaxCtxIdNum;\r
+ UINT8 SysDataTagUnitSize;\r
+ UINT8 SysDataResUnitSize;\r
+ UINT8 SupSecRemovalTypes;\r
+ UINT16 SupMemTypes;\r
+ UINT32 SysCodeMaxNumAllocUnits;\r
+ UINT16 SupCodeCapAdjFac;\r
+ UINT32 NonPersMaxNumAllocUnits;\r
+ UINT16 NonPersCapAdjFac;\r
+ UINT32 Enhance1MaxNumAllocUnits;\r
+ UINT16 Enhance1CapAdjFac;\r
+ UINT32 Enhance2MaxNumAllocUnits;\r
+ UINT16 Enhance2CapAdjFac;\r
+ UINT32 Enhance3MaxNumAllocUnits;\r
+ UINT16 Enhance3CapAdjFac;\r
+ UINT32 Enhance4MaxNumAllocUnits;\r
+ UINT16 Enhance4CapAdjFac;\r
} UFS_GEOMETRY_DESC;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.5 - Unit Descriptor\r
//\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- UINT8 UnitIdx;\r
- UINT8 LunEn;\r
- UINT8 BootLunId;\r
- UINT8 LunWriteProt;\r
- UINT8 LunQueueDep;\r
- UINT8 Rsvd1;\r
- UINT8 MemType;\r
- UINT8 DataReliability;\r
- UINT8 LogicBlkSize;\r
- UINT64 LogicBlkCount;\r
- UINT32 EraseBlkSize;\r
- UINT8 ProvisionType;\r
- UINT64 PhyMemResCount;\r
- UINT16 CtxCap;\r
- UINT8 LargeUnitGranularity;\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ UINT8 UnitIdx;\r
+ UINT8 LunEn;\r
+ UINT8 BootLunId;\r
+ UINT8 LunWriteProt;\r
+ UINT8 LunQueueDep;\r
+ UINT8 Rsvd1;\r
+ UINT8 MemType;\r
+ UINT8 DataReliability;\r
+ UINT8 LogicBlkSize;\r
+ UINT64 LogicBlkCount;\r
+ UINT32 EraseBlkSize;\r
+ UINT8 ProvisionType;\r
+ UINT64 PhyMemResCount;\r
+ UINT16 CtxCap;\r
+ UINT8 LargeUnitGranularity;\r
} UFS_UNIT_DESC;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.6 - RPMB Unit Descriptor\r
//\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- UINT8 UnitIdx;\r
- UINT8 LunEn;\r
- UINT8 BootLunId;\r
- UINT8 LunWriteProt;\r
- UINT8 LunQueueDep;\r
- UINT8 Rsvd1;\r
- UINT8 MemType;\r
- UINT8 Rsvd2;\r
- UINT8 LogicBlkSize;\r
- UINT64 LogicBlkCount;\r
- UINT32 EraseBlkSize;\r
- UINT8 ProvisionType;\r
- UINT64 PhyMemResCount;\r
- UINT8 Rsvd3[3];\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ UINT8 UnitIdx;\r
+ UINT8 LunEn;\r
+ UINT8 BootLunId;\r
+ UINT8 LunWriteProt;\r
+ UINT8 LunQueueDep;\r
+ UINT8 Rsvd1;\r
+ UINT8 MemType;\r
+ UINT8 Rsvd2;\r
+ UINT8 LogicBlkSize;\r
+ UINT64 LogicBlkCount;\r
+ UINT32 EraseBlkSize;\r
+ UINT8 ProvisionType;\r
+ UINT64 PhyMemResCount;\r
+ UINT8 Rsvd3[3];\r
} UFS_RPMB_UNIT_DESC;\r
\r
typedef struct {\r
- UINT16 Value:10;\r
- UINT16 Rsvd1:4;\r
- UINT16 Unit:2;\r
+ UINT16 Value : 10;\r
+ UINT16 Rsvd1 : 4;\r
+ UINT16 Unit : 2;\r
} UFS_POWER_PARAM_ELEMENT;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.7 - Power Parameter Descriptor\r
//\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- UFS_POWER_PARAM_ELEMENT ActiveIccLevelVcc[16];\r
- UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ[16];\r
- UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ2[16];\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ UFS_POWER_PARAM_ELEMENT ActiveIccLevelVcc[16];\r
+ UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ[16];\r
+ UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ2[16];\r
} UFS_POWER_DESC;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.8 - InterConnect Descriptor\r
//\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- UINT16 UniProVer;\r
- UINT16 MphyVer;\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ UINT16 UniProVer;\r
+ UINT16 MphyVer;\r
} UFS_INTER_CONNECT_DESC;\r
\r
//\r
// UFS 2.0 Spec Section 14.1.6.9 - 14.1.6.12 - String Descriptor\r
//\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescType;\r
- CHAR16 Unicode[126];\r
+ UINT8 Length;\r
+ UINT8 DescType;\r
+ CHAR16 Unicode[126];\r
} UFS_STRING_DESC;\r
\r
//\r
// UFS 2.0 Spec Section 14.2 - Attributes\r
//\r
typedef enum {\r
- UfsAttrBootLunEn = 0x00,\r
- UfsAttrCurPowerMode = 0x02,\r
- UfsAttrActiveIccLevel = 0x03,\r
- UfsAttrOutOfOrderDataEn = 0x04,\r
- UfsAttrBgOpStatus = 0x05,\r
- UfsAttrPurgeStatus = 0x06,\r
- UfsAttrMaxDataInSize = 0x07,\r
- UfsAttrMaxDataOutSize = 0x08,\r
- UfsAttrDynCapNeeded = 0x09,\r
- UfsAttrRefClkFreq = 0x0a,\r
- UfsAttrConfigDescLock = 0x0b,\r
- UfsAttrMaxNumOfRtt = 0x0c,\r
- UfsAttrExceptionEvtCtrl = 0x0d,\r
- UfsAttrExceptionEvtSts = 0x0e,\r
- UfsAttrSecondsPassed = 0x0f,\r
- UfsAttrContextConf = 0x10,\r
- UfsAttrCorrPrgBlkNum = 0x11\r
+ UfsAttrBootLunEn = 0x00,\r
+ UfsAttrCurPowerMode = 0x02,\r
+ UfsAttrActiveIccLevel = 0x03,\r
+ UfsAttrOutOfOrderDataEn = 0x04,\r
+ UfsAttrBgOpStatus = 0x05,\r
+ UfsAttrPurgeStatus = 0x06,\r
+ UfsAttrMaxDataInSize = 0x07,\r
+ UfsAttrMaxDataOutSize = 0x08,\r
+ UfsAttrDynCapNeeded = 0x09,\r
+ UfsAttrRefClkFreq = 0x0a,\r
+ UfsAttrConfigDescLock = 0x0b,\r
+ UfsAttrMaxNumOfRtt = 0x0c,\r
+ UfsAttrExceptionEvtCtrl = 0x0d,\r
+ UfsAttrExceptionEvtSts = 0x0e,\r
+ UfsAttrSecondsPassed = 0x0f,\r
+ UfsAttrContextConf = 0x10,\r
+ UfsAttrCorrPrgBlkNum = 0x11\r
} UFS_ATTR_IDN;\r
\r
typedef enum {\r
- UfsNoData = 0,\r
- UfsDataOut = 1,\r
- UfsDataIn = 2,\r
+ UfsNoData = 0,\r
+ UfsDataOut = 1,\r
+ UfsDataIn = 2,\r
UfsDdReserved\r
} UFS_DATA_DIRECTION;\r
\r
-\r
#pragma pack()\r
\r
#endif\r
-\r
projects / mirror_edk2.git / blobdiff