UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol interface\r
for upper layer application to execute UFS-supported SCSI cmds.\r
\r
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "UfsPassThru.h"\r
\r
+/**\r
+ Read 32bits data from specified UFS MMIO register.\r
+\r
+ @param[in] Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA data structure.\r
+ @param[in] Offset The offset within the UFS Host Controller MMIO space to start\r
+ the memory operation.\r
+ @param[out] Value The data buffer to store.\r
+\r
+ @retval EFI_TIMEOUT The operation is time out.\r
+ @retval EFI_SUCCESS The operation succeeds.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+UfsMmioRead32 (\r
+ IN UFS_PASS_THRU_PRIVATE_DATA *Private,\r
+ IN UINTN Offset,\r
+ OUT UINT32 *Value\r
+ )\r
+{\r
+ EDKII_UFS_HOST_CONTROLLER_PROTOCOL *UfsHc;\r
+ EFI_STATUS Status;\r
+\r
+ UfsHc = Private->UfsHostController;\r
+\r
+ Status = UfsHc->Read (UfsHc, EfiUfsHcWidthUint32, Offset, 1, Value);\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Write 32bits data to specified UFS MMIO register.\r
+\r
+ @param[in] Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA data structure.\r
+ @param[in] Offset The offset within the UFS Host Controller MMIO space to start\r
+ the memory operation.\r
+ @param[in] Value The data to write.\r
+\r
+ @retval EFI_TIMEOUT The operation is time out.\r
+ @retval EFI_SUCCESS The operation succeeds.\r
+ @retval Others The operation fails.\r
+\r
+**/\r
+EFI_STATUS\r
+UfsMmioWrite32 (\r
+ IN UFS_PASS_THRU_PRIVATE_DATA *Private,\r
+ IN UINTN Offset,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ EDKII_UFS_HOST_CONTROLLER_PROTOCOL *UfsHc;\r
+ EFI_STATUS Status;\r
+\r
+ UfsHc = Private->UfsHostController;\r
+\r
+ Status = UfsHc->Write (UfsHc, EfiUfsHcWidthUint32, Offset, 1, &Value);\r
+\r
+ return Status;\r
+}\r
+\r
/**\r
Wait for the value of the specified system memory set to the test value.\r
\r
- @param Address The system memory address to test.\r
- @param MaskValue The mask value of memory.\r
- @param TestValue The test value of memory.\r
- @param Timeout The time out value for wait memory set, uses 100ns as a unit.\r
+ @param[in] Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA data structure.\r
+ @param[in] Offset The offset within the UFS Host Controller MMIO space to start\r
+ the memory operation.\r
+ @param[in] MaskValue The mask value of memory.\r
+ @param[in] TestValue The test value of memory.\r
+ @param[in] Timeout The time out value for wait memory set, uses 100ns as a unit.\r
\r
@retval EFI_TIMEOUT The system memory setting is time out.\r
@retval EFI_SUCCESS The system memory is correct set.\r
+ @retval Others The operation fails.\r
\r
**/\r
EFI_STATUS\r
-EFIAPI\r
UfsWaitMemSet (\r
- IN UINTN Address,\r
- IN UINT32 MaskValue,\r
- IN UINT32 TestValue,\r
- IN UINT64 Timeout\r
+ IN UFS_PASS_THRU_PRIVATE_DATA *Private,\r
+ IN UINTN Offset,\r
+ IN UINT32 MaskValue,\r
+ IN UINT32 TestValue,\r
+ IN UINT64 Timeout\r
)\r
{\r
UINT32 Value;\r
UINT64 Delay;\r
BOOLEAN InfiniteWait;\r
+ EFI_STATUS Status;\r
\r
if (Timeout == 0) {\r
InfiniteWait = TRUE;\r
//\r
// Access PCI MMIO space to see if the value is the tested one.\r
//\r
- Value = MmioRead32 (Address) & MaskValue;\r
+ Status = UfsMmioRead32 (Private, Offset, &Value);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Value &= MaskValue;\r
\r
if (Value == TestValue) {\r
return EFI_SUCCESS;\r
@param[in] Slot The slot to be started.\r
\r
**/\r
-VOID\r
+EFI_STATUS\r
UfsStartExecCmd (\r
IN UFS_PASS_THRU_PRIVATE_DATA *Private,\r
IN UINT8 Slot\r
) \r
{\r
- UINTN UfsHcBase;\r
- UINTN Address;\r
UINT32 Data;\r
+ EFI_STATUS Status;\r
\r
- UfsHcBase = Private->UfsHcBase;\r
+ Status = UfsMmioRead32 (Private, UFS_HC_UTRLRSR_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- Address = UfsHcBase + UFS_HC_UTRLRSR_OFFSET; \r
- Data = MmioRead32 (Address);\r
if ((Data & UFS_HC_UTRLRSR) != UFS_HC_UTRLRSR) {\r
- MmioWrite32 (Address, UFS_HC_UTRLRSR);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTRLRSR_OFFSET, UFS_HC_UTRLRSR);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTRLDBR_OFFSET, BIT0 << Slot);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
}\r
\r
- Address = UfsHcBase + UFS_HC_UTRLDBR_OFFSET;\r
- MmioWrite32 (Address, BIT0 << Slot);\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
@param[in] Slot The slot to be stop.\r
\r
**/\r
-VOID\r
+EFI_STATUS\r
UfsStopExecCmd (\r
IN UFS_PASS_THRU_PRIVATE_DATA *Private,\r
IN UINT8 Slot\r
) \r
{\r
- UINTN UfsHcBase;\r
- UINTN Address;\r
UINT32 Data;\r
+ EFI_STATUS Status;\r
\r
- UfsHcBase = Private->UfsHcBase;\r
+ Status = UfsMmioRead32 (Private, UFS_HC_UTRLDBR_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- Address = UfsHcBase + UFS_HC_UTRLDBR_OFFSET; \r
- Data = MmioRead32 (Address);\r
if ((Data & (BIT0 << Slot)) != 0) {\r
- Address = UfsHcBase + UFS_HC_UTRLCLR_OFFSET; \r
- Data = MmioRead32 (Address);\r
- MmioWrite32 (Address, (Data & ~(BIT0 << Slot)));\r
+ Status = UfsMmioRead32 (Private, UFS_HC_UTRLCLR_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTRLCLR_OFFSET, Data & ~(BIT0 << Slot));\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
}\r
+\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
UFS_DEVICE_MANAGEMENT_REQUEST_PACKET Packet;\r
UINT8 Slot;\r
UTP_TRD *Trd;\r
- UINTN Address;\r
UTP_QUERY_RESP_UPIU *QueryResp;\r
UINT32 CmdDescSize;\r
UINT16 ReturnDataSize;\r
//\r
// Wait for the completion of the transfer request.\r
// \r
- Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET; \r
- Status = UfsWaitMemSet (Address, BIT0, 0, Packet.Timeout);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);\r
if (EFI_ERROR (Status)) {\r
goto Exit;\r
}\r
UFS_DEVICE_MANAGEMENT_REQUEST_PACKET Packet;\r
UINT8 Slot;\r
UTP_TRD *Trd;\r
- UINTN Address;\r
UTP_QUERY_RESP_UPIU *QueryResp;\r
UINT32 CmdDescSize;\r
UINT32 ReturnData;\r
//\r
// Wait for the completion of the transfer request.\r
// \r
- Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET; \r
- Status = UfsWaitMemSet (Address, BIT0, 0, Packet.Timeout);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);\r
if (EFI_ERROR (Status)) {\r
goto Exit;\r
}\r
UFS_DEVICE_MANAGEMENT_REQUEST_PACKET Packet;\r
UINT8 Slot;\r
UTP_TRD *Trd;\r
- UINTN Address;\r
UTP_QUERY_RESP_UPIU *QueryResp;\r
UINT32 CmdDescSize;\r
VOID *CmdDescHost;\r
//\r
// Wait for the completion of the transfer request.\r
// \r
- Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET; \r
- Status = UfsWaitMemSet (Address, BIT0, 0, Packet.Timeout);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet.Timeout);\r
if (EFI_ERROR (Status)) {\r
goto Exit;\r
}\r
UTP_TRD *Trd;\r
UTP_NOP_IN_UPIU *NopInUpiu;\r
UINT32 CmdDescSize;\r
- UINTN Address;\r
VOID *CmdDescHost;\r
VOID *CmdDescMapping;\r
EDKII_UFS_HOST_CONTROLLER_PROTOCOL *UfsHc;\r
//\r
// Wait for the completion of the transfer request.\r
// \r
- Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET; \r
- Status = UfsWaitMemSet (Address, BIT0, 0, UFS_TIMEOUT);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, UFS_TIMEOUT);\r
if (EFI_ERROR (Status)) {\r
goto Exit;\r
}\r
EFI_STATUS Status;\r
UINT8 Slot;\r
UTP_TRD *Trd;\r
- UINTN Address;\r
UINT32 CmdDescSize;\r
UTP_RESPONSE_UPIU *Response;\r
UINT16 SenseDataLen;\r
\r
//\r
// Wait for the completion of the transfer request.\r
- // \r
- Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET; \r
- Status = UfsWaitMemSet (Address, BIT0, 0, Packet->Timeout);\r
+ // \r
+ Status = UfsWaitMemSet (Private, UFS_HC_UTRLDBR_OFFSET, BIT0, 0, Packet->Timeout);\r
if (EFI_ERROR (Status)) {\r
goto Exit;\r
}\r
)\r
{\r
EFI_STATUS Status;\r
- UINTN Address;\r
UINT32 Data;\r
- UINTN UfsHcBase;\r
\r
- UfsHcBase = Private->UfsHcBase;\r
- Address = UfsHcBase + UFS_HC_IS_OFFSET;\r
- Data = MmioRead32 (Address);\r
+ Status = UfsMmioRead32 (Private, UFS_HC_IS_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
if ((Data & UFS_HC_IS_UCCS) == UFS_HC_IS_UCCS) {\r
//\r
// Clear IS.BIT10 UIC Command Completion Status (UCCS) at first.\r
//\r
- MmioWrite32 (Address, Data);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_IS_OFFSET, Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
}\r
\r
//\r
// only after all the UIC command argument registers (UICCMDARG1, UICCMDARG2 and UICCMDARG3)\r
// are set.\r
//\r
- Address = UfsHcBase + UFS_HC_UCMD_ARG1_OFFSET;\r
- MmioWrite32 (Address, Arg1);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, Arg1);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- Address = UfsHcBase + UFS_HC_UCMD_ARG2_OFFSET;\r
- MmioWrite32 (Address, Arg2);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, Arg2);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- Address = UfsHcBase + UFS_HC_UCMD_ARG3_OFFSET;\r
- MmioWrite32 (Address, Arg3);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, Arg3);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
//\r
// Host software shall only set the UICCMD if HCS.UCRDY is set to 1.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_STATUS_OFFSET;\r
- Status = UfsWaitMemSet (Address, UFS_HC_HCS_UCRDY, UFS_HC_HCS_UCRDY, UFS_TIMEOUT);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_STATUS_OFFSET, UFS_HC_HCS_UCRDY, UFS_HC_HCS_UCRDY, UFS_TIMEOUT);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- Address = UfsHcBase + UFS_HC_UIC_CMD_OFFSET;\r
- MmioWrite32 (Address, (UINT32)UicOpcode);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, (UINT32)UicOpcode);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
//\r
// UFS 2.0 spec section 5.3.1 Offset:0x20 IS.Bit10 UIC Command Completion Status (UCCS)\r
// This bit is set to '1' by the host controller upon completion of a UIC command. \r
//\r
- Address = UfsHcBase + UFS_HC_IS_OFFSET;\r
- Data = MmioRead32 (Address);\r
- Status = UfsWaitMemSet (Address, UFS_HC_IS_UCCS, UFS_HC_IS_UCCS, UFS_TIMEOUT);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_IS_OFFSET, UFS_HC_IS_UCCS, UFS_HC_IS_UCCS, UFS_TIMEOUT);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
if (UicOpcode != UfsUicDmeReset) {\r
- Address = UfsHcBase + UFS_HC_UCMD_ARG2_OFFSET;\r
- Data = MmioRead32 (Address);\r
+ Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
if ((Data & 0xFF) != 0) {\r
DEBUG_CODE_BEGIN();\r
DumpUicCmdExecResult (UicOpcode, (UINT8)(Data & 0xFF));\r
//\r
// Check value of HCS.DP and make sure that there is a device attached to the Link.\r
//\r
- Address = UfsHcBase + UFS_HC_STATUS_OFFSET; \r
- Data = MmioRead32 (Address);\r
+ Status = UfsMmioRead32 (Private, UFS_HC_STATUS_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
if ((Data & UFS_HC_HCS_DP) == 0) {\r
- Address = UfsHcBase + UFS_HC_IS_OFFSET;\r
- Status = UfsWaitMemSet (Address, UFS_HC_IS_ULSS, UFS_HC_IS_ULSS, UFS_TIMEOUT);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_IS_OFFSET, UFS_HC_IS_ULSS, UFS_HC_IS_ULSS, UFS_TIMEOUT);\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
}\r
)\r
{\r
EFI_STATUS Status;\r
- UINTN Address;\r
UINT32 Data;\r
\r
//\r
//\r
// Reinitialize the UFS host controller if HCE bit of HC register is set.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_ENABLE_OFFSET;\r
- Data = MmioRead32 (Address);\r
+ Status = UfsMmioRead32 (Private, UFS_HC_ENABLE_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
if ((Data & UFS_HC_HCE_EN) == UFS_HC_HCE_EN) {\r
//\r
// Write a 0 to the HCE register at first to disable the host controller.\r
//\r
- MmioWrite32 (Address, 0);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_ENABLE_OFFSET, 0);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
//\r
// Wait until HCE is read as '0' before continuing.\r
//\r
- Status = UfsWaitMemSet (Address, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
}\r
//\r
// Write a 1 to the HCE register to enable the UFS host controller.\r
//\r
- MmioWrite32 (Address, UFS_HC_HCE_EN);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
//\r
// Wait until HCE is read as '1' before continuing.\r
//\r
- Status = UfsWaitMemSet (Address, UFS_HC_HCE_EN, UFS_HC_HCE_EN, UFS_TIMEOUT);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN, UFS_HC_HCE_EN, UFS_TIMEOUT);\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
}\r
IN UFS_PASS_THRU_PRIVATE_DATA *Private\r
)\r
{\r
- UINTN Address;\r
UINT32 Data;\r
UINT8 Nutmrs;\r
VOID *CmdDescHost;\r
CmdDescHost = NULL;\r
CmdDescMapping = NULL;\r
CmdDescPhyAddr = 0;\r
- Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET; \r
- Data = MmioRead32 (Address);\r
+\r
+ Status = UfsMmioRead32 (Private, UFS_HC_CAP_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
Private->Capabilities = Data;\r
\r
//\r
// Program the UTP Task Management Request List Base Address and UTP Task Management\r
// Request List Base Address with a 64-bit address allocated at step 6.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_UTMRLBA_OFFSET; \r
- MmioWrite32 (Address, (UINT32)(UINTN)CmdDescPhyAddr);\r
- Address = Private->UfsHcBase + UFS_HC_UTMRLBAU_OFFSET; \r
- MmioWrite32 (Address, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLBA_OFFSET, (UINT32)(UINTN)CmdDescPhyAddr);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLBAU_OFFSET, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
Private->UtpTmrlBase = CmdDescHost;\r
Private->Nutmrs = Nutmrs;\r
Private->TmrlMapping = CmdDescMapping;\r
// Enable the UTP Task Management Request List by setting the UTP Task Management\r
// Request List RunStop Register (UTMRLRSR) to '1'.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET; \r
- MmioWrite32 (Address, UFS_HC_UTMRLRSR);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLRSR_OFFSET, UFS_HC_UTMRLRSR);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
return EFI_SUCCESS;\r
}\r
IN UFS_PASS_THRU_PRIVATE_DATA *Private\r
)\r
{\r
- UINTN Address;\r
UINT32 Data;\r
UINT8 Nutrs;\r
VOID *CmdDescHost;\r
CmdDescHost = NULL;\r
CmdDescMapping = NULL;\r
CmdDescPhyAddr = 0;\r
- Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET; \r
- Data = MmioRead32 (Address);\r
+\r
+ Status = UfsMmioRead32 (Private, UFS_HC_CAP_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
Private->Capabilities = Data;\r
\r
//\r
// Program the UTP Transfer Request List Base Address and UTP Transfer Request List\r
// Base Address with a 64-bit address allocated at step 8.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_UTRLBA_OFFSET; \r
- MmioWrite32 (Address, (UINT32)(UINTN)CmdDescPhyAddr);\r
- Address = Private->UfsHcBase + UFS_HC_UTRLBAU_OFFSET; \r
- MmioWrite32 (Address, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTRLBA_OFFSET, (UINT32)(UINTN)CmdDescPhyAddr);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTRLBAU_OFFSET, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
Private->UtpTrlBase = CmdDescHost;\r
Private->Nutrs = Nutrs; \r
Private->TrlMapping = CmdDescMapping;\r
// Enable the UTP Transfer Request List by setting the UTP Transfer Request List\r
// RunStop Register (UTRLRSR) to '1'.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET; \r
- MmioWrite32 (Address, UFS_HC_UTRLRSR);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTRLRSR_OFFSET, UFS_HC_UTRLRSR);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
return EFI_SUCCESS;\r
}\r
)\r
{\r
EFI_STATUS Status;\r
- UINTN Address;\r
UINT32 Data;\r
\r
//\r
// Enable the UTP Task Management Request List by setting the UTP Task Management\r
// Request List RunStop Register (UTMRLRSR) to '1'.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET; \r
- MmioWrite32 (Address, 0);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTMRLRSR_OFFSET, 0);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
//\r
// Enable the UTP Transfer Request List by setting the UTP Transfer Request List\r
// RunStop Register (UTRLRSR) to '1'.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET; \r
- MmioWrite32 (Address, 0);\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_UTRLRSR_OFFSET, 0);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
//\r
// Write a 0 to the HCE register in order to disable the host controller.\r
//\r
- Address = Private->UfsHcBase + UFS_HC_ENABLE_OFFSET;\r
- Data = MmioRead32 (Address);\r
+ Status = UfsMmioRead32 (Private, UFS_HC_ENABLE_OFFSET, &Data);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
ASSERT ((Data & UFS_HC_HCE_EN) == UFS_HC_HCE_EN);\r
- MmioWrite32 (Address, 0);\r
+\r
+ Status = UfsMmioWrite32 (Private, UFS_HC_ENABLE_OFFSET, 0);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
//\r
// Wait until HCE is read as '0' before continuing.\r
//\r
- Status = UfsWaitMemSet (Address, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);\r
+ Status = UfsWaitMemSet (Private, UFS_HC_ENABLE_OFFSET, UFS_HC_HCE_EN, 0, UFS_TIMEOUT);\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
}\r
projects / mirror_edk2.git / blobdiff