Update DXE Core to be compatible with PI 1.2 SMM Drivers.

[mirror_edk2.git] / MdeModulePkg / Core / Dxe / Event / Tpl.c

diff --git a/MdeModulePkg/Core/Dxe/Event/Tpl.c b/MdeModulePkg/Core/Dxe/Event/Tpl.c
index e99cb7355c40d5aa2f7c9387039b8adc0bc8a798..265204f3160d591e4860ab8ba747f6c6c16ad27b 100644 (file)
--- a/MdeModulePkg/Core/Dxe/Event/Tpl.c
+++ b/MdeModulePkg/Core/Dxe/Event/Tpl.c
@@ -1,7 +1,7 @@
 /** @file\r
   Task priority (TPL) functions.\r
 \r
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
 All rights reserved. This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -12,8 +12,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 **/\r
 \r
-#include <DxeMain.h>\r
-\r
+#include "DxeMain.h"\r
+#include "Event.h"\r
 \r
 /**\r
   Set Interrupt State.\r
@@ -26,45 +26,27 @@ CoreSetInterruptState (
   IN BOOLEAN      Enable\r
   )\r
 {\r
-  if (gCpu != NULL) {\r
-    if (Enable) {\r
-      gCpu->EnableInterrupt(gCpu);\r
-    } else {\r
-      gCpu->DisableInterrupt(gCpu);\r
-    }\r
+  EFI_STATUS  Status;\r
+  BOOLEAN     InSmm;\r
+  \r
+  if (gCpu == NULL) {\r
+    return;\r
   }\r
-}\r
-\r
-//\r
-// Return the highest set bit\r
-//\r
-\r
-/**\r
-  Return the highest set bit.\r
-\r
-  @param  Number  The value to check\r
-\r
-  @return Bit position of the highest set bit\r
-\r
-**/\r
-UINTN\r
-CoreHighestSetBit (\r
-  IN UINTN     Number\r
-  )\r
-{\r
-  UINTN   Msb;\r
-\r
-  Msb = 31;\r
-  while ((Msb > 0) && ((Number & (UINTN)(1 << Msb)) == 0)) {\r
-    Msb--;\r
+  if (!Enable) {\r
+    gCpu->DisableInterrupt (gCpu);\r
+    return;\r
+  }\r
+  if (gSmmBase2 == NULL) {\r
+    gCpu->EnableInterrupt (gCpu);\r
+    return;\r
+  }\r
+  Status = gSmmBase2->InSmm (gSmmBase2, &InSmm);\r
+  if (!EFI_ERROR (Status) && !InSmm) {\r
+    gCpu->EnableInterrupt(gCpu);\r
   }\r
-\r
-  return Msb;\r
 }\r
 \r
 \r
-\r
-\r
 /**\r
   Raise the task priority level to the new level.\r
   High level is implemented by disabling processor interrupts.\r
@@ -135,9 +117,8 @@ CoreRestoreTpl (
   //\r
   // Dispatch any pending events\r
   //\r
-\r
-  while ((-2 << NewTpl) & gEventPending) {\r
-    gEfiCurrentTpl = CoreHighestSetBit (gEventPending);\r
+  while (((-2 << NewTpl) & gEventPending) != 0) {\r
+    gEfiCurrentTpl = HighBitSet64 (gEventPending);\r
     if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r
       CoreSetInterruptState (TRUE);\r
     }\r