-/*++\r
+/** @file\r
+ Ia32-specific functionality for DxeLoad.\r
\r
-Copyright (c) 2006, Intel Corporation\r
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-Module Name:\r
-\r
- DxeLoadFunc.c\r
-\r
-Abstract:\r
-\r
- Ia32-specifc functionality for DxeLoad.\r
-\r
---*/\r
-\r
-//\r
-// Include common header file for this module.\r
-//\r
-#include "CommonHeader.h"\r
+**/\r
\r
#include "DxeIpl.h"\r
#include "VirtualMemory.h"\r
\r
+#define IDT_ENTRY_COUNT 32\r
+\r
//\r
// Global Descriptor Table (GDT)\r
//\r
-GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries [] = {\r
-/* selector { Global Segment Descriptor } */ \r
-/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor \r
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries[] = {\r
+/* selector { Global Segment Descriptor } */\r
+/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor\r
/* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear data segment descriptor\r
/* 0x10 */ {{0xffff, 0, 0, 0xf, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear code segment descriptor\r
/* 0x18 */ {{0xffff, 0, 0, 0x3, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor\r
(UINTN) gGdtEntries\r
};\r
\r
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR gLidtDescriptor = {\r
+ sizeof (X64_IDT_GATE_DESCRIPTOR) * IDT_ENTRY_COUNT - 1,\r
+ 0\r
+};\r
+\r
+/**\r
+ Transfers control to DxeCore.\r
+\r
+ This function performs a CPU architecture specific operations to execute\r
+ the entry point of DxeCore with the parameters of HobList.\r
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.\r
+\r
+ @param DxeCoreEntryPoint The entry point of DxeCore.\r
+ @param HobList The start of HobList passed to DxeCore.\r
+\r
+**/\r
VOID\r
HandOffToDxeCore (\r
IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,\r
- IN EFI_PEI_HOB_POINTERS HobList,\r
- IN EFI_PEI_PPI_DESCRIPTOR *EndOfPeiSignal\r
+ IN EFI_PEI_HOB_POINTERS HobList\r
)\r
{\r
EFI_STATUS Status;\r
EFI_PHYSICAL_ADDRESS BaseOfStack;\r
EFI_PHYSICAL_ADDRESS TopOfStack;\r
UINTN PageTables;\r
+ X64_IDT_GATE_DESCRIPTOR *IdtTable;\r
+ UINTN SizeOfTemplate;\r
+ VOID *TemplateBase;\r
+ EFI_PHYSICAL_ADDRESS VectorAddress;\r
+ UINT32 Index;\r
\r
Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {\r
//\r
- // Compute the top of the stack we were allocated, which is used to load X64 dxe core. \r
+ // Compute the top of the stack we were allocated, which is used to load X64 dxe core.\r
// Pre-allocate a 32 bytes which confroms to x64 calling convention.\r
//\r
- // The first four parameters to a function are passed in rcx, rdx, r8 and r9. \r
- // Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the \r
- // register parameters is reserved on the stack, in case the called function \r
- // wants to spill them; this is important if the function is variadic. \r
+ // The first four parameters to a function are passed in rcx, rdx, r8 and r9.\r
+ // Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the\r
+ // register parameters is reserved on the stack, in case the called function\r
+ // wants to spill them; this is important if the function is variadic.\r
//\r
TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;\r
\r
//\r
- // X64 Calling Conventions requires that the stack must be aligned to 16 bytes\r
+ // x64 Calling Conventions requires that the stack must be aligned to 16 bytes\r
//\r
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);\r
\r
//\r
// Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA\r
- // memory, it may be corrupted when copying FV to high-end memory \r
+ // memory, it may be corrupted when copying FV to high-end memory\r
//\r
AsmWriteGdtr (&gGdt);\r
//\r
PageTables = CreateIdentityMappingPageTables ();\r
\r
//\r
- // End of PEI phase singal\r
+ // End of PEI phase signal\r
//\r
- Status = PeiServicesInstallPpi (EndOfPeiSignal);\r
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
AsmWriteCr3 (PageTables);\r
- //\r
- // Go to Long Mode. Interrupts will not get turned on until the CPU AP is loaded.\r
+\r
+ //\r
+ // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r
+ //\r
+ UpdateStackHob (BaseOfStack, STACK_SIZE);\r
+\r
+ SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);\r
+\r
+ Status = PeiServicesAllocatePages (\r
+ EfiBootServicesData,\r
+ EFI_SIZE_TO_PAGES((SizeOfTemplate + sizeof (X64_IDT_GATE_DESCRIPTOR)) * IDT_ENTRY_COUNT),\r
+ &VectorAddress\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ IdtTable = (X64_IDT_GATE_DESCRIPTOR *) (UINTN) (VectorAddress + SizeOfTemplate * IDT_ENTRY_COUNT);\r
+ for (Index = 0; Index < IDT_ENTRY_COUNT; Index++) {\r
+ IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;\r
+ IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;\r
+ IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;\r
+\r
+ IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;\r
+ IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));\r
+ IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));\r
+ IdtTable[Index].Reserved = 0;\r
+\r
+ CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);\r
+ AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);\r
+\r
+ VectorAddress += SizeOfTemplate;\r
+ }\r
+\r
+ gLidtDescriptor.Base = (UINTN) IdtTable;\r
+\r
+ //\r
+ // Disable interrupt of Debug timer, since new IDT table cannot handle it.\r
+ //\r
+ SaveAndSetDebugTimerInterrupt (FALSE);\r
+\r
+ AsmWriteIdtr (&gLidtDescriptor);\r
+\r
+ //\r
+ // Go to Long Mode and transfer control to DxeCore.\r
+ // Interrupts will not get turned on until the CPU AP is loaded.\r
// Call x64 drivers passing in single argument, a pointer to the HOBs.\r
- // \r
+ //\r
AsmEnablePaging64 (\r
SYS_CODE64_SEL,\r
DxeCoreEntryPoint,\r
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);\r
\r
//\r
- // End of PEI phase singal\r
+ // End of PEI phase signal\r
//\r
- Status = PeiServicesInstallPpi (EndOfPeiSignal);\r
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r
ASSERT_EFI_ERROR (Status);\r
\r
+ //\r
+ // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r
+ //\r
+ UpdateStackHob (BaseOfStack, STACK_SIZE);\r
+\r
+ //\r
+ // Transfer the control to the entry point of DxeCore.\r
+ //\r
SwitchStack (\r
(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r
HobList.Raw,\r
NULL,\r
(VOID *) (UINTN) TopOfStack\r
);\r
- } \r
+ }\r
}\r
\r
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