enter Long Mode (x64 64-bit mode).\r
\r
While we make a 1:1 mapping (identity mapping) for all physical pages \r
- we still need to use the MTRR's to ensure that the cachability attirbutes\r
+ we still need to use the MTRR's to ensure that the cachability attributes\r
for all memory regions is correct.\r
\r
The basic idea is to use 2MB page table entries where ever possible. If\r
more granularity of cachability is required then 4K page tables are used.\r
\r
References:\r
- 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
- 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
- 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
+ 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
+ 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
+ 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
\r
Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
#include "DxeIpl.h"\r
#include "VirtualMemory.h"\r
\r
-\r
-\r
-\r
-\r
-\r
/**\r
Allocates and fills in the Page Directory and Page Table Entries to\r
establish a 1:1 Virtual to Physical mapping.\r
table entries to the physical \r
address space. \r
\r
- @return EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created\r
+ @return The address of 4 level page map.\r
\r
**/\r
UINTN\r