/** @file\r
- x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
+ x64 Virtual Memory Management Services in the form of an IA-32 driver.\r
Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
enter Long Mode (x64 64-bit mode).\r
\r
- While we make a 1:1 mapping (identity mapping) for all physical pages \r
+ While we make a 1:1 mapping (identity mapping) for all physical pages\r
we still need to use the MTRR's to ensure that the cachability attributes\r
for all memory regions is correct.\r
\r
2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
-**/ \r
+**/\r
\r
#include "DxeIpl.h"\r
#include "VirtualMemory.h"\r
The function will check if page table entry should be splitted to smaller\r
granularity.\r
\r
+ @param Address Physical memory address.\r
+ @param Size Size of the given physical memory.\r
+ @param StackBase Base address of stack.\r
+ @param StackSize Size of stack.\r
+\r
@retval TRUE Page table should be split.\r
@retval FALSE Page table should not be split.\r
**/\r
//\r
// The smaller granularity of page must be needed.\r
//\r
+ ASSERT (Level > 1);\r
+\r
NewPageTable = AllocatePageTableMemory (1);\r
ASSERT (NewPageTable != NULL);\r
\r
++EntryIndex) {\r
NewPageTable[EntryIndex] = PhysicalAddress | AddressEncMask |\r
IA32_PG_P | IA32_PG_RW;\r
- if (Level > 1) {\r
+ if (Level > 2) {\r
NewPageTable[EntryIndex] |= IA32_PG_PS;\r
}\r
- PhysicalAddress += LevelSize[Level];\r
+ PhysicalAddress += LevelSize[Level - 1];\r
}\r
\r
PageTable[Index] = (UINT64)(UINTN)NewPageTable | AddressEncMask |\r
IN EFI_PHYSICAL_ADDRESS StackBase,\r
IN UINTN StackSize\r
)\r
-{ \r
+{\r
UINT32 RegEax;\r
UINT32 RegEdx;\r
UINT8 PhysicalAddressBits;\r
}\r
\r
//\r
- // Pre-allocate big pages to avoid later allocations. \r
+ // Pre-allocate big pages to avoid later allocations.\r
//\r
if (!Page1GSupport) {\r
TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
\r
if (Page1GSupport) {\r
PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;\r
- \r
+\r
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize)) {\r
Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize);\r
//\r
// Each Directory Pointer entries points to a page of Page Directory entires.\r
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
- // \r
+ //\r
PageDirectoryEntry = (VOID *) BigPageAddress;\r
BigPageAddress += SIZE_4KB;\r
\r