MdeModulePkg: Clean up source files

[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.h

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
index 26a2100f0b804c619835c1d9f0422b15a6c01822..85457ff93712af6bc0ec2dbe00514102bc579ad9 100644 (file)
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
@@ -1,5 +1,5 @@
 /** @file\r
-  x64 Long Mode Virtual Memory Management Definitions  \r
+  x64 Long Mode Virtual Memory Management Definitions\r
 \r
   References:\r
     1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
@@ -7,7 +7,7 @@
     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
 \r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -18,7 +18,7 @@ http://opensource.org/licenses/bsd-license.php
 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
-**/  \r
+**/\r
 #ifndef _VIRTUAL_MEMORY_H_\r
 #define _VIRTUAL_MEMORY_H_\r
 \r
@@ -110,7 +110,7 @@ typedef union {
     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1 \r
+    UINT64  MustBe1:1;                // Must be 1\r
     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
     UINT64  Available:3;              // Available for use by system software\r
     UINT64  PAT:1;                    //\r
@@ -134,7 +134,7 @@ typedef union {
     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1 \r
+    UINT64  MustBe1:1;                // Must be 1\r
     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
     UINT64  Available:3;              // Available for use by system software\r
     UINT64  PAT:1;                    //\r
@@ -148,11 +148,37 @@ typedef union {
 \r
 #pragma pack()\r
 \r
+#define CR0_WP                      BIT16\r
+\r
 #define IA32_PG_P                   BIT0\r
 #define IA32_PG_RW                  BIT1\r
+#define IA32_PG_PS                  BIT7\r
 \r
+#define PAGING_PAE_INDEX_MASK       0x1FF\r
+\r
+#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
 #define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
 \r
+#define PAGING_L1_ADDRESS_SHIFT     12\r
+#define PAGING_L2_ADDRESS_SHIFT     21\r
+#define PAGING_L3_ADDRESS_SHIFT     30\r
+#define PAGING_L4_ADDRESS_SHIFT     39\r
+\r
+#define PAGING_PML4E_NUMBER         4\r
+\r
+#define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
+#define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB\r
+#define PAGE_TABLE_POOL_UNIT_PAGES  EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
+#define PAGE_TABLE_POOL_ALIGN_MASK  \\r
+  (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
+\r
+typedef struct {\r
+  VOID            *NextPool;\r
+  UINTN           Offset;\r
+  UINTN           FreePages;\r
+} PAGE_TABLE_POOL;\r
+\r
 /**\r
   Enable Execute Disable Bit.\r
 \r
@@ -197,9 +223,9 @@ CreateIdentityMappingPageTables (
 \r
 \r
 /**\r
- \r
+\r
   Fix up the vector number in the vector code.\r
- \r
+\r
   @param VectorBase   Base address of the vector handler.\r
   @param VectorNum    Index of vector.\r
 \r
@@ -213,11 +239,11 @@ AsmVectorFixup (
 \r
 \r
 /**\r
- \r
+\r
   Get the information of vector template.\r
-  \r
+\r
   @param TemplateBase   Base address of the template code.\r
- \r
+\r
   @return               Size of the Template code.\r
 \r
 **/\r
@@ -252,4 +278,39 @@ IsNullDetectionEnabled (
   VOID\r
   );\r
 \r
-#endif \r
+/**\r
+  Prevent the memory pages used for page table from been overwritten.\r
+\r
+  @param[in] PageTableBase    Base address of page table (CR3).\r
+  @param[in] Level4Paging     Level 4 paging flag.\r
+\r
+**/\r
+VOID\r
+EnablePageTableProtection (\r
+  IN  UINTN     PageTableBase,\r
+  IN  BOOLEAN   Level4Paging\r
+  );\r
+\r
+/**\r
+  This API provides a way to allocate memory for page table.\r
+\r
+  This API can be called more than once to allocate memory for page tables.\r
+\r
+  Allocates the number of 4KB pages and returns a pointer to the allocated\r
+  buffer. The buffer returned is aligned on a 4KB boundary.\r
+\r
+  If Pages is 0, then NULL is returned.\r
+  If there is not enough memory remaining to satisfy the request, then NULL is\r
+  returned.\r
+\r
+  @param  Pages                 The number of 4 KB pages to allocate.\r
+\r
+  @return A pointer to the allocated buffer or NULL if allocation fails.\r
+\r
+**/\r
+VOID *\r
+AllocatePageTableMemory (\r
+  IN UINTN           Pages\r
+  );\r
+\r
+#endif\r