MdeModulePkg/DxeIpl: Mark page table as read-only

[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.h

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
index 7c9bb49e3e2cffe60797403bb0bdc6131c7074a1..e7959b2cf01b9a73fa8c7d8b02a4c19a92784db5 100644 (file)
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
@@ -7,7 +7,7 @@
     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
 \r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -148,11 +148,37 @@ typedef union {
 \r
 #pragma pack()\r
 \r
+#define CR0_WP                      BIT16\r
+\r
 #define IA32_PG_P                   BIT0\r
 #define IA32_PG_RW                  BIT1\r
+#define IA32_PG_PS                  BIT7\r
+\r
+#define PAGING_PAE_INDEX_MASK       0x1FF\r
 \r
+#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
 #define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
 \r
+#define PAGING_L1_ADDRESS_SHIFT     12\r
+#define PAGING_L2_ADDRESS_SHIFT     21\r
+#define PAGING_L3_ADDRESS_SHIFT     30\r
+#define PAGING_L4_ADDRESS_SHIFT     39\r
+\r
+#define PAGING_PML4E_NUMBER         4\r
+\r
+#define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
+#define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB\r
+#define PAGE_TABLE_POOL_UNIT_PAGES  EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
+#define PAGE_TABLE_POOL_ALIGN_MASK  \\r
+  (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
+\r
+typedef struct {\r
+  VOID            *NextPool;\r
+  UINTN           Offset;\r
+  UINTN           FreePages;\r
+} PAGE_TABLE_POOL;\r
+\r
 /**\r
   Enable Execute Disable Bit.\r
 \r
@@ -227,5 +253,64 @@ AsmGetVectorTemplatInfo (
   OUT   VOID  **TemplateBase\r
   );\r
 \r
+/**\r
+  Clear legacy memory located at the first 4K-page.\r
+\r
+  This function traverses the whole HOB list to check if memory from 0 to 4095\r
+  exists and has not been allocated, and then clear it if so.\r
+\r
+  @param HobStart         The start of HobList passed to DxeCore.\r
+\r
+**/\r
+VOID\r
+ClearFirst4KPage (\r
+  IN  VOID *HobStart\r
+  );\r
+\r
+/**\r
+  Return configure status of NULL pointer detection feature.\r
+\r
+  @return TRUE   NULL pointer detection feature is enabled\r
+  @return FALSE  NULL pointer detection feature is disabled\r
+**/\r
+BOOLEAN\r
+IsNullDetectionEnabled (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Prevent the memory pages used for page table from been overwritten.\r
+\r
+  @param[in] PageTableBase    Base address of page table (CR3).\r
+  @param[in] Level4Paging     Level 4 paging flag.\r
+\r
+**/\r
+VOID\r
+EnablePageTableProtection (\r
+  IN  UINTN     PageTableBase,\r
+  IN  BOOLEAN   Level4Paging\r
+  );\r
+\r
+/**\r
+  This API provides a way to allocate memory for page table.\r
+\r
+  This API can be called more than once to allocate memory for page tables.\r
+\r
+  Allocates the number of 4KB pages and returns a pointer to the allocated\r
+  buffer. The buffer returned is aligned on a 4KB boundary.\r
+\r
+  If Pages is 0, then NULL is returned.\r
+  If there is not enough memory remaining to satisfy the request, then NULL is\r
+  returned.\r
+\r
+  @param  Pages                 The number of 4 KB pages to allocate.\r
+\r
+  @return A pointer to the allocated buffer or NULL if allocation fails.\r
+\r
+**/\r
+VOID *\r
+AllocatePageTableMemory (\r
+  IN UINTN           Pages\r
+  );\r
 \r
 #endif \r