UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / MdeModulePkg / Include / Ppi / AtaController.h

diff --git a/MdeModulePkg/Include/Ppi/AtaController.h b/MdeModulePkg/Include/Ppi/AtaController.h
index a24b496f9c0e8559149c898a0a0cd223682bc47b..0096f7bae0744fd4f97e037fe0e53f24b18a8896 100644 (file)
--- a/MdeModulePkg/Include/Ppi/AtaController.h
+++ b/MdeModulePkg/Include/Ppi/AtaController.h
@@ -4,14 +4,7 @@
 \r
 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 \r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions\r
-of the BSD License which accompanies this distribution.  The\r
-full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -37,7 +30,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
 /// This is designed for old generation chipset with PATA/SATA controllers.\r
 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
-#define PEI_ICH_IDE_NONE        0x00\r
+#define PEI_ICH_IDE_NONE  0x00\r
 \r
 ///\r
 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
@@ -45,7 +38,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
 /// This is designed for old generation chipset with PATA/SATA controllers.\r
 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
-#define PEI_ICH_IDE_PRIMARY     0x01\r
+#define PEI_ICH_IDE_PRIMARY  0x01\r
 \r
 ///\r
 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
@@ -53,7 +46,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
 /// This is designed for old generation chipset with PATA/SATA controllers.\r
 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
-#define PEI_ICH_IDE_SECONDARY   0x02\r
+#define PEI_ICH_IDE_SECONDARY  0x02\r
 \r
 ///\r
 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
@@ -61,7 +54,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
 /// This is designed for old generation chipset with PATA/SATA controllers.\r
 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
-#define PEI_ICH_SATA_NONE       0x04\r
+#define PEI_ICH_SATA_NONE  0x04\r
 \r
 ///\r
 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
@@ -69,7 +62,7 @@ typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
 /// This is designed for old generation chipset with PATA/SATA controllers.\r
 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
-#define PEI_ICH_SATA_PRIMARY    0x08\r
+#define PEI_ICH_SATA_PRIMARY  0x08\r
 \r
 ///\r
 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
@@ -86,11 +79,11 @@ typedef struct {
   ///\r
   /// Base I/O port address of the IDE controller's command block\r
   ///\r
-  UINT16  CommandBlockBaseAddr;\r
+  UINT16    CommandBlockBaseAddr;\r
   ///\r
   /// Base I/O port address of the IDE controller's control block\r
   ///\r
-  UINT16  ControlBlockBaseAddr;\r
+  UINT16    ControlBlockBaseAddr;\r
 } IDE_REGS_BASE_ADDR;\r
 \r
 /**\r
@@ -151,12 +144,10 @@ UINT32
 /// retrieves the base I/O port addresses to the enabled IDE and SATA channels.\r
 ///\r
 struct _PEI_ATA_CONTROLLER_PPI {\r
-  PEI_ENABLE_ATA          EnableAtaChannel;\r
-  GET_IDE_REGS_BASE_ADDR  GetIdeRegsBaseAddr;\r
+  PEI_ENABLE_ATA            EnableAtaChannel;\r
+  GET_IDE_REGS_BASE_ADDR    GetIdeRegsBaseAddr;\r
 };\r
 \r
-extern EFI_GUID gPeiAtaControllerPpiGuid;\r
+extern EFI_GUID  gPeiAtaControllerPpiGuid;\r
 \r
 #endif\r
-\r
-\r