/** @file\r
Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve\r
the base I/O port address for each of the enabled IDE and SATA channels.\r
- \r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions\r
-of the BSD License which accompanies this distribution. The\r
-full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#define _PEI_ATA_CONTROLLER_PPI_H_\r
\r
///\r
-/// Global ID for the PEI_ATA_CONTROLLER_PPI. \r
+/// Global ID for the PEI_ATA_CONTROLLER_PPI.\r
///\r
#define PEI_ATA_CONTROLLER_PPI_GUID \\r
{ \\r
typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;\r
\r
///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
-/// disable the IDE channels. \r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
+/// disable the IDE channels.\r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_IDE_NONE 0x00\r
+#define PEI_ICH_IDE_NONE 0x00\r
\r
///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// enable the Primary IDE channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_IDE_PRIMARY 0x01\r
+#define PEI_ICH_IDE_PRIMARY 0x01\r
\r
///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// enable the Secondary IDE channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_IDE_SECONDARY 0x02\r
+#define PEI_ICH_IDE_SECONDARY 0x02\r
\r
///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// disable the SATA channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_SATA_NONE 0x04\r
+#define PEI_ICH_SATA_NONE 0x04\r
\r
///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// enable the Primary SATA channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
-#define PEI_ICH_SATA_PRIMARY 0x08\r
+#define PEI_ICH_SATA_PRIMARY 0x08\r
\r
///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
/// enable the Secondary SATA channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
///\r
#define PEI_ICH_SATA_SECONDARY 0x010\r
\r
///\r
/// Base I/O port address of the IDE controller's command block\r
///\r
- UINT16 CommandBlockBaseAddr;\r
+ UINT16 CommandBlockBaseAddr;\r
///\r
/// Base I/O port address of the IDE controller's control block\r
///\r
- UINT16 ControlBlockBaseAddr;\r
+ UINT16 ControlBlockBaseAddr;\r
} IDE_REGS_BASE_ADDR;\r
\r
/**\r
Sets IDE and SATA channels to an enabled or disabled state.\r
\r
This service enables or disables the IDE and SATA channels specified by ChannelMask.\r
- It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy. \r
- The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function. \r
+ It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy.\r
+ The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function.\r
\r
If the new state is set, then EFI_SUCCESS is returned. If the new state can\r
not be set, then EFI_DEVICE_ERROR is returned.\r
\r
@param[in] PeiServices The pointer to the PEI Services Table.\r
@param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r
- @param[in] ChannelMask The bitmask that identifies the IDE and SATA channels to \r
- enable or disable. This paramter is optional. \r
+ @param[in] ChannelMask The bitmask that identifies the IDE and SATA channels to\r
+ enable or disable. This parameter is optional.\r
\r
@retval EFI_SUCCESS The IDE or SATA channels were enabled or disabled successfully.\r
@retval EFI_DEVICE_ERROR The IDE or SATA channels could not be enabled or disabled.\r
);\r
\r
/**\r
- Retrieves the I/O port base addresses for command and control registers of the \r
+ Retrieves the I/O port base addresses for command and control registers of the\r
enabled IDE/SATA channels.\r
\r
This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O\r
port base addresses for the command and control registers of the IDE and SATA\r
- channels that were previously enabled in EnableAtaChannel(). The number of \r
+ channels that were previously enabled in EnableAtaChannel(). The number of\r
enabled IDE and SATA channels is returned.\r
\r
@param[in] PeiServices The pointer to the PEI Services Table.\r
@param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r
- @param[out] IdeRegsBaseAddr The pointer to caller allocated space to return the \r
- I/O port base addresses of the IDE and SATA channels \r
+ @param[out] IdeRegsBaseAddr The pointer to caller allocated space to return the\r
+ I/O port base addresses of the IDE and SATA channels\r
that were previosuly enabled with EnableAtaChannel().\r
\r
@return The number of enabled IDE and SATA channels in the platform.\r
(EFIAPI *GET_IDE_REGS_BASE_ADDR)(\r
IN EFI_PEI_SERVICES **PeiServices,\r
IN PEI_ATA_CONTROLLER_PPI *This,\r
- OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr \r
+ OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr\r
);\r
\r
///\r
/// retrieves the base I/O port addresses to the enabled IDE and SATA channels.\r
///\r
struct _PEI_ATA_CONTROLLER_PPI {\r
- PEI_ENABLE_ATA EnableAtaChannel;\r
- GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;\r
+ PEI_ENABLE_ATA EnableAtaChannel;\r
+ GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr;\r
};\r
\r
-extern EFI_GUID gPeiAtaControllerPpiGuid;\r
+extern EFI_GUID gPeiAtaControllerPpiGuid;\r
\r
#endif\r
-\r
-\r
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