#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \\r
{ 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } }\r
\r
-#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x2\r
+#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x3\r
\r
typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE;\r
\r
-//\r
-// Bus timing modes\r
-//\r
+#define EDKII_SD_MMC_BUS_WIDTH_IGNORE MAX_UINT8\r
+#define EDKII_SD_MMC_CLOCK_FREQ_IGNORE MAX_UINT32\r
+#define EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE MAX_UINT8\r
+\r
+typedef enum {\r
+ SdDriverStrengthTypeB = 0,\r
+ SdDriverStrengthTypeA,\r
+ SdDriverStrengthTypeC,\r
+ SdDriverStrengthTypeD,\r
+ SdDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE\r
+} SD_DRIVER_STRENGTH_TYPE;\r
+\r
typedef enum {\r
+ EmmcDriverStrengthType0 = 0,\r
+ EmmcDriverStrengthType1,\r
+ EmmcDriverStrengthType2,\r
+ EmmcDriverStrengthType3,\r
+ EmmcDriverStrengthType4,\r
+ EmmcDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE\r
+} EMMC_DRIVER_STRENGTH_TYPE;\r
+\r
+typedef union {\r
+ SD_DRIVER_STRENGTH_TYPE Sd;\r
+ EMMC_DRIVER_STRENGTH_TYPE Emmc;\r
+} EDKII_SD_MMC_DRIVER_STRENGTH;\r
+\r
+typedef struct {\r
+ //\r
+ // The target width of the bus. If user tells driver to ignore it\r
+ // or specifies unsupported width driver will choose highest supported\r
+ // bus width for a given mode.\r
+ //\r
+ UINT8 BusWidth;\r
+ //\r
+ // The target clock frequency of the bus in MHz. If user tells driver to ignore\r
+ // it or specifies unsupported frequency driver will choose highest supported\r
+ // clock frequency for a given mode.\r
+ //\r
+ UINT32 ClockFreq;\r
+ //\r
+ // The target driver strength of the bus. If user tells driver to\r
+ // ignore it or specifies unsupported driver strength, driver will\r
+ // default to Type0 for eMMC cards and TypeB for SD cards. Driver strength\r
+ // setting is only considered if chosen bus timing supports them.\r
+ //\r
+ EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;\r
+} EDKII_SD_MMC_OPERATING_PARAMETERS;\r
+\r
+typedef enum {\r
+ SdMmcSdDs,\r
+ SdMmcSdHs,\r
SdMmcUhsSdr12,\r
SdMmcUhsSdr25,\r
SdMmcUhsSdr50,\r
- SdMmcUhsSdr104,\r
SdMmcUhsDdr50,\r
+ SdMmcUhsSdr104,\r
SdMmcMmcLegacy,\r
SdMmcMmcHsSdr,\r
SdMmcMmcHsDdr,\r
EdkiiSdMmcInitHostPost,\r
EdkiiSdMmcUhsSignaling,\r
EdkiiSdMmcSwitchClockFreqPost,\r
+ EdkiiSdMmcGetOperatingParam\r
} EDKII_SD_MMC_PHASE_TYPE;\r
\r
/**\r
-\r
Override function for SDHCI capability bits\r
\r
@param[in] ControllerHandle The EFI_HANDLE of the controller.\r
);\r
\r
/**\r
-\r
Override function for SDHCI controller operations\r
\r
@param[in] ControllerHandle The EFI_HANDLE of the controller.\r