MdeModulePkg: Add new structure for the PCI Root Bridge Info Hob

[mirror_edk2.git] / MdeModulePkg / Include / UniversalPayload / PciRootBridges.h

diff --git a/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h b/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h
new file mode 100644 (file)
index 0000000..3a7aae8
--- /dev/null
+++ b/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h
@@ -0,0 +1,91 @@
+/** @file\r
+  This file defines the structure for the PCI Root Bridges.\r
+\r
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+  @par Revision Reference:\r
+    - Universal Payload Specification 0.75 (https://universalpayload.github.io/documentation/)\r
+**/\r
+\r
+#ifndef UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_\r
+#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_\r
+\r
+#include <UniversalPayload/UniversalPayload.h>\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// (Base > Limit) indicates an aperture is not available.\r
+//\r
+typedef struct {\r
+  //\r
+  // Base and Limit are the device address instead of host address when\r
+  // Translation is not zero\r
+  //\r
+  UINT64 Base;\r
+  UINT64 Limit;\r
+  //\r
+  // According to UEFI 2.7, Device Address = Host Address + Translation,\r
+  // so Translation = Device Address - Host Address.\r
+  // On platforms where Translation is not zero, the subtraction is probably to\r
+  // be performed with UINT64 wrap-around semantics, for we may translate an\r
+  // above-4G host address into a below-4G device address for legacy PCIe device\r
+  // compatibility.\r
+  //\r
+  // NOTE: The alignment of Translation is required to be larger than any BAR\r
+  // alignment in the same root bridge, so that the same alignment can be\r
+  // applied to both device address and host address, which simplifies the\r
+  // situation and makes the current resource allocation code in generic PCI\r
+  // host bridge driver still work.\r
+  //\r
+  UINT64 Translation;\r
+} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE;\r
+\r
+///\r
+/// Payload PCI Root Bridge Information HOB\r
+///\r
+typedef struct {\r
+  UINT32                                     Segment;               ///< Segment number.\r
+  UINT64                                     Supports;              ///< Supported attributes.\r
+                                                                    ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
+                                                                    ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+  UINT64                                     Attributes;            ///< Initial attributes.\r
+                                                                    ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
+                                                                    ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+  BOOLEAN                                    DmaAbove4G;            ///< DMA above 4GB memory.\r
+                                                                    ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r
+  BOOLEAN                                    NoExtendedConfigSpace; ///< When FALSE, the root bridge supports\r
+                                                                    ///< Extended (4096-byte) Configuration Space.\r
+                                                                    ///< When TRUE, the root bridge supports\r
+                                                                    ///< 256-byte Configuration Space only.\r
+  UINT64                                     AllocationAttributes;  ///< Allocation attributes.\r
+                                                                    ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r
+                                                                    ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r
+                                                                    ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus;                   ///< Bus aperture which can be used by the root bridge.\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io;                    ///< IO aperture which can be used by the root bridge.\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem;                   ///< MMIO aperture below 4GB which can be used by the root bridge.\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G;            ///< MMIO aperture above 4GB which can be used by the root bridge.\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem;                  ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;           ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r
+  UINT32                                     HID;                   ///< PnP hardware ID of the root bridge. This value must match the corresponding\r
+                                                                    ///< _HID in the ACPI name space.\r
+  UINT32                                     UID;                   ///< Unique ID that is required by ACPI if two devices have the same _HID.\r
+                                                                    ///< This value must also match the corresponding _UID/_HID pair in the ACPI name space.\r
+} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE;\r
+\r
+typedef struct {\r
+  UNIVERSAL_PAYLOAD_GENERIC_HEADER   Header;\r
+  BOOLEAN                            ResourceAssigned;\r
+  UINT8                              Count;\r
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE  RootBridge[0];\r
+} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES;\r
+\r
+#pragma pack()\r
+\r
+#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1\r
+\r
+extern GUID gUniversalPayloadPciRootBridgeInfoGuid;\r
+\r
+#endif // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_\r