#\r
AuthVariableLib|Include/Library/AuthVariableLib.h\r
\r
+ ## @libraryclass Provides variable check services and database management.\r
+ #\r
+ VarCheckLib|Include/Library/VarCheckLib.h\r
+\r
+ ## @libraryclass Provides services to get variable error flag and do platform variable cleanup.\r
+ #\r
+ PlatformVarCleanupLib|Include/Library/PlatformVarCleanupLib.h\r
+ \r
+ ## @libraryclass Provides services to get do the file explorer.\r
+ #\r
+ FileExplorerLib|Include/Library/FileExplorerLib.h\r
+\r
+ ## @libraryclass Provides image decoding service.\r
+ #\r
+ ImageDecoderLib|Include/Library/ImageDecoderLib.h\r
+\r
+ ## @libraryclass Provides interfaces about logo display.\r
+ #\r
+ BootLogoLib|Include/Library/BootLogoLib.h\r
+\r
[Guids]\r
## MdeModule package token space guid\r
# Include/Guid/MdeModulePkgTokenSpace.h\r
\r
## Include/Guid/HiiBootMaintenanceFormset.h\r
gEfiIfrBootMaintenanceGuid = { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a, 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 }}\r
+\r
+ gEfiIfrFrontPageGuid = { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a, 0xa3, 0x0f, 0xdc, 0x4b, 0x44, 0x1e } }\r
+\r
\r
[Ppis]\r
## Include/Ppi/AtaController.h\r
## Include/Protocol/SmmReadyToBoot.h\r
gEdkiiSmmReadyToBootProtocolGuid = { 0x6e057ecf, 0xfa99, 0x4f39, { 0x95, 0xbc, 0x59, 0xf9, 0x92, 0x1d, 0x17, 0xe4 } }\r
\r
+ ## Include/Protocol/PlatformLogo.h\r
+ gEdkiiPlatformLogoProtocolGuid = { 0x9b517978, 0xeba1, 0x44e7, { 0xba, 0x65, 0x7c, 0x2c, 0xd0, 0x8b, 0xf8, 0xe9 } }\r
+\r
+ ## Include/Protocol/FileExplorer.h\r
+ gEfiFileExplorerProtocolGuid = { 0x2C03C536, 0x4594, 0x4515, { 0x9E, 0x7A, 0xD3, 0xD2, 0x04, 0xFE, 0x13, 0x63 } }\r
+\r
#\r
# [Error.gEfiMdeModulePkgTokenSpaceGuid]\r
# 0x80000001 | Invalid value provided.\r
# @Prompt Enable S3 performance data support.\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwarePerformanceDataTableS3Support|TRUE|BOOLEAN|0x00010064\r
\r
+ ## Indicates if Serial device uses half hand shake.<BR><BR>\r
+ # TRUE - Serial device uses half hand shake.<BR>\r
+ # FALSE - Serial device doesn't use half hand shake.<BR>\r
+ # @Prompt Enable Serial device Half Hand Shake\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHalfHandshake|FALSE|BOOLEAN|0x00010073\r
+\r
[PcdsFeatureFlag.IA32, PcdsFeatureFlag.X64]\r
## Indicates if DxeIpl should switch to long mode to enter DXE phase.\r
# It is assumed that 64-bit DxeCore is built in firmware if it is true; otherwise 32-bit DxeCore\r
# @Prompt Shadow Peim On S3 Boot. \r
gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|FALSE|BOOLEAN|0x30001028\r
\r
+ ## Indicates if to shadow PEIM and PeiCore after memory is ready.<BR><BR>\r
+ # This PCD is used on other boot path except for S3 boot. \r
+ # TRUE - Shadow PEIM and PeiCore after memory is ready.<BR>\r
+ # FALSE - Not shadow PEIM after memory is ready.<BR>\r
+ # @Prompt Shadow Peim and PeiCore on boot\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnBoot|TRUE|BOOLEAN|0x30001029\r
+\r
## The mask is used to control memory profile behavior.<BR><BR>\r
# BIT0 - Enable UEFI memory profile.<BR>\r
# BIT1 - Enable SMRAM profile.<BR>\r
# @Prompt Pci Serial Device Info\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xFF}|VOID*|0x00010067\r
\r
+ ## PCI Serial Parameters. It is an array of VendorID, DeviceID, ClockRate, Offset,\r
+ # BarIndex, RegisterStride, ReceiveFifoDepth, TransmitFifoDepth information that \r
+ # describes the parameters of special PCI serial devices.\r
+ # Each array entry is 24-byte in length. The array is terminated\r
+ # by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a\r
+ # standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF.\r
+ # The C style structure is defined as below:\r
+ # typedef struct {\r
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ # UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ # UINT64 Offset; ///< The byte offset into to the BAR\r
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT8 Reserved[2];\r
+ # } PCI_SERIAL_PARAMETER;\r
+ # It contains zero or more instances of the above structure.\r
+ # For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs\r
+ # to contain two instances of the above structure, with the VendorId and DeviceId\r
+ # equals to the Device ID and Vendor ID of the device; If the PCI device uses the\r
+ # first two BARs to support two UARTs, BarIndex of first instance equals to 0 and\r
+ # BarIndex of second one equals to 1; If the PCI device uses the first BAR to\r
+ # support both UARTs, BarIndex of both instance equals to 0, Offset of first\r
+ # instance equals to 0 and Offset of second one equals to a value bigger than or\r
+ # equal to 8.\r
+ # For certain UART whose register needs to be accessed in DWORD aligned address,\r
+ # RegisterStride equals to 4.\r
+ # @Prompt Pci Serial Parameters\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0xFF, 0xFF}|VOID*|0x00010071\r
+\r
## Serial Port Extended Transmit FIFO Size. The default is 64 bytes. \r
# @Prompt Serial Port Extended Transmit FIFO Size in Bytes\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|64|UINT32|0x00010068\r
## The number of bytes between registers in serial device. The default is 1 byte.\r
# @Prompt Serial Port Register Stride in Bytes\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1|UINT32|0x0001006d\r
- \r
+\r
+ ## This PCD to include the driver guid of VFR drivers for VarCheckHiiBin generation.<BR><BR>\r
+ # Default is gZeroGuid that means no VFR driver will be parsed for VarCheckHiiBin generation.<BR>\r
+ # If it is set to an all FFs GUID, it means all modules in all FVs will be parsed for VarCheckHiiBin generation.<BR>\r
+ # @Prompt Driver guid array of VFR drivers for VarCheckHiiBin generation.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVarCheckVfrDriverGuidArray|{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x3000103A\r
+\r
[PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
## This PCD defines the Console output row. The default value is 25 according to UEFI spec.\r
# This PCD could be set to 0 then console output would be at max column and max row.\r
# @Prompt SATA spin-up delay time in second for recovery path.\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSataSpinUpDelayInSecForRecoveryPath|15|UINT16|0x0001005B\r
\r
- ## This PCD is used to specify memory size with page number for a pre-allocated ACPI NVS memory to hold\r
- # runtime created S3 boot script entries. The default page number is 2. When changing the value of this\r
- # PCD, the platform developer should make sure the memory size is large enough to hold the S3 boot\r
- # script node created in runtime phase.\r
+ ## This PCD is used to specify memory size with page number for a pre-allocated ACPI reserved memory\r
+ # to hold runtime(after SmmReadyToLock) created S3 boot script entries. The default page number is 2.\r
+ # When changing the value of this PCD, the platform developer should make sure the memory size is\r
+ # large enough to hold the S3 boot script node created in runtime(after SmmReadyToLock) phase.\r
# @Prompt Reserved page number for S3 Boot Script Runtime Table.\r
gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptRuntimeTableReservePageNumber|0x2|UINT16|0x0001005C\r
\r
# @Prompt Default Creator Revision for ACPI table creation.\r
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038\r
\r
+ ## Indicates if to set NX for stack.<BR><BR>\r
+ # For the DxeIpl and the DxeCore are both X64, set NX for stack feature also require PcdDxeIplBuildPageTables be TRUE.<BR>\r
+ # For the DxeIpl and the DxeCore are both IA32 (PcdDxeIplSwitchToLongMode is FALSE), set NX for stack feature also require\r
+ # IA32 PAE is supported and Execute Disable Bit is available.<BR>\r
+ # TRUE - to set NX for stack.<BR>\r
+ # FALSE - Not to set NX for stack.<BR>\r
+ # @Prompt Set NX for stack.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|FALSE|BOOLEAN|0x0001006f\r
+\r
[PcdsPatchableInModule]\r
## Specify memory size with page number for PEI code when\r
# Loading Module at Fixed Address feature is enabled.\r
projects / mirror_edk2.git / blobdiff