NetworkPkg: Remove a CopyMem to speed up the HTTP boot download.

[mirror_edk2.git] / MdeModulePkg / MdeModulePkg.dec

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index e2e0b75cdb31aaf8ce2bf63d74a908b1956ecf79..a96229676d06f38eee524610c025bba448eef96a 100644 (file)
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -983,19 +983,19 @@
   #  Each array entry is 24-byte in length. The array is terminated\r
   #  by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a\r
   #  standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF.\r
-  #  The C style structure is defined as below:\r
-  #  typedef struct {\r
-  #    UINT16  VendorId;          ///< Vendor ID to match the PCI device.  The value 0xFFFF terminates the list of entries.\r
-  #    UINT16  DeviceId;          ///< Device ID to match the PCI device\r
-  #    UINT32  ClockRate;         ///< UART clock rate.  Set to 0 for default clock rate of 1843200 Hz\r
-  #    UINT64  Offset;            ///< The byte offset into to the BAR\r
-  #    UINT8   BarIndex;          ///< Which BAR to get the UART base address\r
-  #    UINT8   RegisterStride;    ///< UART register stride in bytes.  Set to 0 for default register stride of 1 byte.\r
-  #    UINT16  ReceiveFifoDepth;  ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
-  #    UINT16  TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
-  #    UINT8   Reserved[2];\r
-  #  } PCI_SERIAL_PARAMETER;\r
-  #  It contains zero or more instances of the above structure.\r
+  #  The C style structure is defined as below:<BR>\r
+  #  typedef struct {<BR>\r
+  #    UINT16  VendorId;          ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.<BR>\r
+  #    UINT16  DeviceId;          ///< Device ID to match the PCI device.<BR>\r
+  #    UINT32  ClockRate;         ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz.<BR>\r
+  #    UINT64  Offset;            ///< The byte offset into to the BAR.<BR>\r
+  #    UINT8   BarIndex;          ///< Which BAR to get the UART base address.<BR>\r
+  #    UINT8   RegisterStride;    ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.<BR>\r
+  #    UINT16  ReceiveFifoDepth;  ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>\r
+  #    UINT16  TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>\r
+  #    UINT8   Reserved[2];<BR>\r
+  #  } PCI_SERIAL_PARAMETER;<BR>\r
+  #  It contains zero or more instances of the above structure.<BR>\r
   #  For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs\r
   #  to contain  two instances of the above structure, with the VendorId and DeviceId\r
   #  equals to the Device ID and Vendor ID of the device; If the PCI device uses the\r
@@ -1003,7 +1003,7 @@
   #  BarIndex of second one equals to 1; If the PCI device uses the first BAR to\r
   #  support both UARTs, BarIndex of both instance equals to 0, Offset of first\r
   #  instance equals to 0 and Offset of second one equals to a value bigger than or\r
-  #  equal to 8.\r
+  #  equal to 8.<BR>\r
   #  For certain UART whose register needs to be accessed in DWORD aligned address,\r
   #  RegisterStride equals to 4.\r
   # @Prompt Pci Serial Parameters\r