"FALSE - Not shadow PEIM after memory is ready.<BR>"\r
\r
#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdShadowPeimOnBoot_PROMPT #language en-US "Shadow Peim on boot"\r
-\r
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHalfHandshake_PROMPT #language en-US "Enable Serial device Half Hand Shake"\r
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHalfHandshake_HELP #language en-US "Indicates if Serial device uses half hand shake.<BR><BR>\n"\r
+ "TRUE - Serial device uses half hand shake.<BR>\n"\r
+ "FALSE - Serial device doesn't use half hand shake.<BR>"\r
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdPciSerialParameters_PROMPT #language en-US "Pci Serial Parameters"\r
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdPciSerialParameters_HELP #language en-US "PCI Serial Parameters. It is an array of VendorID, DeviceID, ClockRate, Offset,\n"\r
+ "BarIndex, RegisterStride, ReceiveFifoDepth, TransmitFifoDepth information that \n"\r
+ "describes the parameters of special PCI serial devices.\n"\r
+ "Each array entry is 24-byte in length. The array is terminated\n"\r
+ "by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a\n"\r
+ "standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF.\n"\r
+ "The C style structure is defined as below:<BR>\n"\r
+ "typedef struct {<BR>\n"\r
+ " UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.<BR>\n"\r
+ " UINT16 DeviceId; ///< Device ID to match the PCI device<BR>\n"\r
+ " UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz<BR>\n"\r
+ " UINT64 Offset; ///< The byte offset into to the BAR<BR>\n"\r
+ " UINT8 BarIndex; ///< Which BAR to get the UART base address<BR>\n"\r
+ " UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.<BR>\n"\r
+ " UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>\n"\r
+ " UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.<BR>\n"\r
+ " UINT8 Reserved[2];<BR>\n"\r
+ "} PCI_SERIAL_PARAMETER;<BR>\n"\r
+ "It contains zero or more instances of the above structure.<BR>\n"\r
+ "For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs\n"\r
+ "to contain two instances of the above structure, with the VendorId and DeviceId\n"\r
+ "equals to the Device ID and Vendor ID of the device; If the PCI device uses the\n"\r
+ "first two BARs to support two UARTs, BarIndex of first instance equals to 0 and\n"\r
+ "BarIndex of second one equals to 1; If the PCI device uses the first BAR to\n"\r
+ "support both UARTs, BarIndex of both instance equals to 0, Offset of first\n"\r
+ "instance equals to 0 and Offset of second one equals to a value bigger than or\n"\r
+ "equal to 8.<BR>\n"\r
+ "For certain UART whose register needs to be accessed in DWORD aligned address,\n"\r
+ "RegisterStride equals to 4.\n"\r
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