/** @file\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
#include <IndustryStandard/PeImage.h>\r
#include "Common/CommonHeader.h"\r
\r
-#ifdef MDE_CPU_IA32 \r
+#ifdef MDE_CPU_IA32\r
\r
#pragma pack(1)\r
\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 MustBe1:1; // Must be 1\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 MustBe1:1; // Must be 1\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r