MdeModulePkg: Apply uncrustify changes

[mirror_edk2.git] / MdeModulePkg / Universal / CapsulePei / Capsule.h

diff --git a/MdeModulePkg/Universal/CapsulePei/Capsule.h b/MdeModulePkg/Universal/CapsulePei/Capsule.h
index 3d9cab02c48500eaca5f7f967eb69ea0471ef532..c16f83a07aa9126c30bc6ec973077051f37dbff5 100644 (file)
--- a/MdeModulePkg/Universal/CapsulePei/Capsule.h
+++ b/MdeModulePkg/Universal/CapsulePei/Capsule.h
@@ -36,7 +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #ifdef MDE_CPU_IA32\r
 \r
-#pragma pack(1)\r
+  #pragma pack(1)\r
 \r
 //\r
 // Page-Map Level-4 Offset (PML4) and\r
@@ -45,18 +45,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Reserved:1;               // Reserved\r
-    UINT64  MustBeZero:2;             // Must Be Zero\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // No Execute bit\r
+    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT64    Reserved             : 1;  // Reserved\r
+    UINT64    MustBeZero           : 2;  // Must Be Zero\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // No Execute bit\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_MAP_AND_DIRECTORY_POINTER;\r
@@ -66,21 +66,21 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:8;             // Must be zero;\r
-    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
+    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page\r
+    UINT64    MustBe1              : 1;  // Must be 1\r
+    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PAT                  : 1;  //\r
+    UINT64    MustBeZero           : 8;  // Must be zero;\r
+    UINT64    PageTableBaseAddress : 31; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_TABLE_ENTRY;\r
@@ -90,32 +90,32 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:17;            // Must be zero;\r
-    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
+    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page\r
+    UINT64    MustBe1              : 1;  // Must be 1\r
+    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PAT                  : 1;  //\r
+    UINT64    MustBeZero           : 17; // Must be zero;\r
+    UINT64    PageTableBaseAddress : 22; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_TABLE_1G_ENTRY;\r
 \r
-#pragma pack()\r
+  #pragma pack()\r
 \r
 typedef\r
 EFI_STATUS\r
 (*COALESCE_ENTRY) (\r
-  SWITCH_32_TO_64_CONTEXT       *EntrypointContext,\r
-  SWITCH_64_TO_32_CONTEXT       *ReturnContext\r
+  SWITCH_32_TO_64_CONTEXT  *EntrypointContext,\r
+  SWITCH_64_TO_32_CONTEXT  *ReturnContext\r
   );\r
 \r
 #endif\r