UINT64 Address;\r
} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
-#pragma pack()\r
-\r
//\r
// Generic Address Space Address IDs\r
//\r
///\r
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
-// \r
-// Ensure proper structure formats\r
-// \r
-#pragma pack(1)\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
-#pragma pack()\r
\r
///\r
/// FADT Version (as defined in ACPI 2.0 spec.)\r
///\r
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03\r
\r
-//\r
-// Fixed ACPI Description Table Boot Architecture Flags\r
-// All other bits are reserved and must be set to 0.\r
-//\r
-#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_2_0_8042 BIT1\r
+///\r
+/// Fixed ACPI Description Table Boot Architecture Flags\r
+/// All other bits are reserved and must be set to 0.\r
+///\r
+#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)\r
+#define EFI_ACPI_2_0_8042 (1 << 1)\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_2_0_WBINVD BIT0\r
-#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_2_0_PROC_C1 BIT2\r
-#define EFI_ACPI_2_0_P_LVL2_UP BIT3\r
-#define EFI_ACPI_2_0_PWR_BUTTON BIT4\r
-#define EFI_ACPI_2_0_SLP_BUTTON BIT5\r
-#define EFI_ACPI_2_0_FIX_RTC BIT6\r
-#define EFI_ACPI_2_0_RTC_S4 BIT7\r
-#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_2_0_DCK_CAP BIT9\r
-#define EFI_ACPI_2_0_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_2_0_SEALED_CASE BIT11\r
-#define EFI_ACPI_2_0_HEADLESS BIT12\r
-#define EFI_ACPI_2_0_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_2_0_WBINVD (1 << 0)\r
+#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)\r
+#define EFI_ACPI_2_0_PROC_C1 (1 << 2)\r
+#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)\r
+#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)\r
+#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)\r
+#define EFI_ACPI_2_0_FIX_RTC (1 << 6)\r
+#define EFI_ACPI_2_0_RTC_S4 (1 << 7)\r
+#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)\r
+#define EFI_ACPI_2_0_DCK_CAP (1 << 9)\r
+#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)\r
+#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)\r
+#define EFI_ACPI_2_0_HEADLESS (1 << 12)\r
+#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)\r
\r
///\r
/// Firmware ACPI Control Structure\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_S4BIOS_F BIT0\r
+#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)\r
\r
///\r
/// IO APIC Structure\r
UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
-//\r
-// Ensure proper structure formats\r
-//\r
-#pragma pack(1)\r
-\r
///\r
/// Local APIC NMI Structure\r
///\r
UINT64 LocalApicAddress;\r
} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
-#pragma pack()\r
-\r
///\r
/// IO SAPIC Structure\r
///\r
///\r
#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\r
\r
+#pragma pack()\r
+\r
#endif\r