/** @file\r
ACPI 6.4 definitions from the ACPI Specification Revision 6.4 Jan, 2021.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7\r
\r
//\r
// Definition for NFIT Structure Header\r
// UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
} EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\r
\r
+//\r
+// Definition for Platform Capabilities Structure\r
+//\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT8 HighestValidCapability;\r
+ UINT8 Reserved_5[3];\r
+ UINT32 Capabilities;\r
+ UINT8 Reserved_12[4];\r
+} EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;\r
+\r
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0\r
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1\r
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2\r
+\r
///\r
/// Secure DEVices Table (SDEV)\r
///\r
//\r
// Boot Error Severity types\r
//\r
-#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTABLE 0x00\r
+#define EFI_ACPI_6_4_ERROR_SEVERITY_RECOVERABLE 0x00\r
#define EFI_ACPI_6_4_ERROR_SEVERITY_FATAL 0x01\r
#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTED 0x02\r
#define EFI_ACPI_6_4_ERROR_SEVERITY_NONE 0x03\r
+//\r
+// The term 'Correctable' is no longer being used as an error severity of the\r
+// reported error since ACPI Specification Version 5.1 Errata B.\r
+// The below macro is considered as deprecated and should no longer be used.\r
+//\r
+#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTABLE 0x00\r
\r
///\r
/// Generic Error Data Entry Definition\r
///\r
#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00\r
#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01\r
-#define EFI_ACPI_6_4_PPTT_TYPE_ID 0x02\r
\r
///\r
/// PPTT Structure Header\r
#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1\r
#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0\r
#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_VALID 0x1\r
\r
///\r
/// Cache Type Structure flags\r
UINT32 CacheId;\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE;\r
\r
-///\r
-/// ID structure\r
-///\r
-typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 VendorId;\r
- UINT64 Level1Id;\r
- UINT64 Level2Id;\r
- UINT16 MajorRev;\r
- UINT16 MinorRev;\r
- UINT16 SpinRev;\r
-} EFI_ACPI_6_4_PPTT_STRUCTURE_ID;\r
-\r
///\r
/// Platform Health Assessment Table (PHAT) Format\r
///\r
///\r
#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\r
\r
+///\r
+/// "APMT" Arm Performance Monitoring Unit Table\r
+///\r
+#define EFI_ACPI_6_4_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T')\r
+\r
///\r
/// "BERT" Boot Error Record Table\r
///\r