// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58\r
// (subject to change as per CXL assigned Vendor ID)\r
//\r
-#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086\r
+#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086\r
\r
//\r
// CXL Flex Bus Device default device and function number\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1\r
//\r
-#define CXL_DEV_DEV 0\r
-#define CXL_DEV_FUNC 0\r
+#define CXL_DEV_DEV 0\r
+#define CXL_DEV_FUNC 0\r
\r
//\r
// Ensure proper structure formats\r
///@{\r
typedef union {\r
struct {\r
- UINT16 CacheCapable : 1; // bit 0\r
- UINT16 IoCapable : 1; // bit 1\r
- UINT16 MemCapable : 1; // bit 2\r
- UINT16 MemHwInitMode : 1; // bit 3\r
- UINT16 HdmCount : 2; // bit 4..5\r
- UINT16 Reserved1 : 8; // bit 6..13\r
- UINT16 ViralCapable : 1; // bit 14\r
- UINT16 Reserved2 : 1; // bit 15\r
+ UINT16 CacheCapable : 1; // bit 0\r
+ UINT16 IoCapable : 1; // bit 1\r
+ UINT16 MemCapable : 1; // bit 2\r
+ UINT16 MemHwInitMode : 1; // bit 3\r
+ UINT16 HdmCount : 2; // bit 4..5\r
+ UINT16 Reserved1 : 8; // bit 6..13\r
+ UINT16 ViralCapable : 1; // bit 14\r
+ UINT16 Reserved2 : 1; // bit 15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 CacheEnable : 1; // bit 0\r
- UINT16 IoEnable : 1; // bit 1\r
- UINT16 MemEnable : 1; // bit 2\r
- UINT16 CacheSfCoverage : 5; // bit 3..7\r
- UINT16 CacheSfGranularity : 3; // bit 8..10\r
- UINT16 CacheCleanEviction : 1; // bit 11\r
- UINT16 Reserved1 : 2; // bit 12..13\r
- UINT16 ViralEnable : 1; // bit 14\r
- UINT16 Reserved2 : 1; // bit 15\r
+ UINT16 CacheEnable : 1; // bit 0\r
+ UINT16 IoEnable : 1; // bit 1\r
+ UINT16 MemEnable : 1; // bit 2\r
+ UINT16 CacheSfCoverage : 5; // bit 3..7\r
+ UINT16 CacheSfGranularity : 3; // bit 8..10\r
+ UINT16 CacheCleanEviction : 1; // bit 11\r
+ UINT16 Reserved1 : 2; // bit 12..13\r
+ UINT16 ViralEnable : 1; // bit 14\r
+ UINT16 Reserved2 : 1; // bit 15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 Reserved1 : 14; // bit 0..13\r
- UINT16 ViralStatus : 1; // bit 14\r
- UINT16 Reserved2 : 1; // bit 15\r
+ UINT16 Reserved1 : 14; // bit 0..13\r
+ UINT16 ViralStatus : 1; // bit 14\r
+ UINT16 Reserved2 : 1; // bit 15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT16 Reserved1 : 1; // bit 0\r
- UINT16 Reserved2 : 1; // bit 1\r
- UINT16 Reserved3 : 1; // bit 2\r
- UINT16 Reserved4 : 13; // bit 3..15\r
+ UINT16 Reserved1 : 1; // bit 0\r
+ UINT16 Reserved2 : 1; // bit 1\r
+ UINT16 Reserved3 : 1; // bit 2\r
+ UINT16 Reserved4 : 13; // bit 3..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;\r
\r
typedef union {\r
struct {\r
- UINT16 Reserved1 : 1; // bit 0\r
- UINT16 Reserved2 : 1; // bit 1\r
- UINT16 Reserved3 : 14; // bit 2..15\r
+ UINT16 Reserved1 : 1; // bit 0\r
+ UINT16 Reserved2 : 1; // bit 1\r
+ UINT16 Reserved3 : 14; // bit 2..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;\r
\r
typedef union {\r
struct {\r
- UINT16 ConfigLock : 1; // bit 0\r
- UINT16 Reserved1 : 15; // bit 1..15\r
+ UINT16 ConfigLock : 1; // bit 0\r
+ UINT16 Reserved1 : 15; // bit 1..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;\r
\r
typedef union {\r
struct {\r
- UINT32 MemorySizeHigh : 32; // bit 0..31\r
+ UINT32 MemorySizeHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryInfoValid : 1; // bit 0\r
- UINT32 MemoryActive : 1; // bit 1\r
- UINT32 MediaType : 3; // bit 2..4\r
- UINT32 MemoryClass : 3; // bit 5..7\r
- UINT32 DesiredInterleave : 3; // bit 8..10\r
- UINT32 Reserved : 17; // bit 11..27\r
- UINT32 MemorySizeLow : 4; // bit 28..31\r
+ UINT32 MemoryInfoValid : 1; // bit 0\r
+ UINT32 MemoryActive : 1; // bit 1\r
+ UINT32 MediaType : 3; // bit 2..4\r
+ UINT32 MemoryClass : 3; // bit 5..7\r
+ UINT32 DesiredInterleave : 3; // bit 8..10\r
+ UINT32 Reserved : 17; // bit 11..27\r
+ UINT32 MemorySizeLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryBaseHigh : 32; // bit 0..31\r
+ UINT32 MemoryBaseHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 28; // bit 0..27\r
- UINT32 MemoryBaseLow : 4; // bit 28..31\r
+ UINT32 Reserved : 28; // bit 0..27\r
+ UINT32 MemoryBaseLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;\r
\r
-\r
typedef union {\r
struct {\r
- UINT32 MemorySizeHigh : 32; // bit 0..31\r
+ UINT32 MemorySizeHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryInfoValid : 1; // bit 0\r
- UINT32 MemoryActive : 1; // bit 1\r
- UINT32 MediaType : 3; // bit 2..4\r
- UINT32 MemoryClass : 3; // bit 5..7\r
- UINT32 DesiredInterleave : 3; // bit 8..10\r
- UINT32 Reserved : 17; // bit 11..27\r
- UINT32 MemorySizeLow : 4; // bit 28..31\r
+ UINT32 MemoryInfoValid : 1; // bit 0\r
+ UINT32 MemoryActive : 1; // bit 1\r
+ UINT32 MediaType : 3; // bit 2..4\r
+ UINT32 MemoryClass : 3; // bit 5..7\r
+ UINT32 DesiredInterleave : 3; // bit 8..10\r
+ UINT32 Reserved : 17; // bit 11..27\r
+ UINT32 MemorySizeLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryBaseHigh : 32; // bit 0..31\r
+ UINT32 MemoryBaseHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 28; // bit 0..27\r
- UINT32 MemoryBaseLow : 4; // bit 28..31\r
+ UINT32 Reserved : 28; // bit 0..27\r
+ UINT32 MemoryBaseLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;\r
\r
//\r
// Flex Bus Device DVSEC ID\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58\r
//\r
-#define FLEX_BUS_DEVICE_DVSEC_ID 0\r
+#define FLEX_BUS_DEVICE_DVSEC_ID 0\r
\r
//\r
// PCIe DVSEC for Flex Bus Device\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95\r
//\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
- CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10\r
- CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12\r
- CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14\r
- CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16\r
- CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18\r
- CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20\r
- UINT16 Reserved; // offset 22\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14\r
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16\r
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20\r
+ UINT16 Reserved; // offset 22\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52\r
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header, 0x00);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability , 0x0A);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl , 0x0C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus , 0x0E);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 , 0x10);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 , 0x12);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock , 0x14);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh , 0x18);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow , 0x1C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh , 0x20);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow , 0x24);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh , 0x28);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow , 0x2C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh , 0x30);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow , 0x34);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability, 0x0A);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl, 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus, 0x0E);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2, 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2, 0x12);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock, 0x14);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh, 0x18);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow, 0x1C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh, 0x20);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow, 0x24);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh, 0x28);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow, 0x2C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh, 0x30);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow, 0x34);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, 0x38);\r
///@}\r
\r
///\r
///@{\r
typedef union {\r
struct {\r
- UINT16 CacheCapable : 1; // bit 0\r
- UINT16 IoCapable : 1; // bit 1\r
- UINT16 MemCapable : 1; // bit 2\r
- UINT16 Reserved : 13; // bit 3..15\r
+ UINT16 CacheCapable : 1; // bit 0\r
+ UINT16 IoCapable : 1; // bit 1\r
+ UINT16 MemCapable : 1; // bit 2\r
+ UINT16 Reserved : 13; // bit 3..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 CacheEnable : 1; // bit 0\r
- UINT16 IoEnable : 1; // bit 1\r
- UINT16 MemEnable : 1; // bit 2\r
- UINT16 CxlSyncBypassEnable : 1; // bit 3\r
- UINT16 DriftBufferEnable : 1; // bit 4\r
- UINT16 Reserved : 3; // bit 5..7\r
- UINT16 Retimer1Present : 1; // bit 8\r
- UINT16 Retimer2Present : 1; // bit 9\r
- UINT16 Reserved2 : 6; // bit 10..15\r
+ UINT16 CacheEnable : 1; // bit 0\r
+ UINT16 IoEnable : 1; // bit 1\r
+ UINT16 MemEnable : 1; // bit 2\r
+ UINT16 CxlSyncBypassEnable : 1; // bit 3\r
+ UINT16 DriftBufferEnable : 1; // bit 4\r
+ UINT16 Reserved : 3; // bit 5..7\r
+ UINT16 Retimer1Present : 1; // bit 8\r
+ UINT16 Retimer2Present : 1; // bit 9\r
+ UINT16 Reserved2 : 6; // bit 10..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 CacheEnable : 1; // bit 0\r
- UINT16 IoEnable : 1; // bit 1\r
- UINT16 MemEnable : 1; // bit 2\r
- UINT16 CxlSyncBypassEnable : 1; // bit 3\r
- UINT16 DriftBufferEnable : 1; // bit 4\r
- UINT16 Reserved : 3; // bit 5..7\r
- UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8\r
- UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9\r
- UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10\r
- UINT16 Reserved2 : 5; // bit 11..15\r
+ UINT16 CacheEnable : 1; // bit 0\r
+ UINT16 IoEnable : 1; // bit 1\r
+ UINT16 MemEnable : 1; // bit 2\r
+ UINT16 CxlSyncBypassEnable : 1; // bit 3\r
+ UINT16 DriftBufferEnable : 1; // bit 4\r
+ UINT16 Reserved : 3; // bit 5..7\r
+ UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8\r
+ UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9\r
+ UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10\r
+ UINT16 Reserved2 : 5; // bit 11..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;\r
\r
//\r
// Flex Bus Port DVSEC ID\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62\r
//\r
-#define FLEX_BUS_PORT_DVSEC_ID 7\r
+#define FLEX_BUS_PORT_DVSEC_ID 7\r
\r
//\r
// PCIe DVSEC for Flex Bus Port\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99\r
//\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
- CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10\r
- CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12\r
- CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10\r
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12\r
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header, 0x00);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability , 0x0A);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl , 0x0C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus , 0x0E);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability, 0x0A);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl, 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus, 0x0E);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, 0x10);\r
///@}\r
\r
///\r
/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1\r
///@{\r
\r
-#define CXL_CAPABILITY_HEADER_OFFSET 0\r
+#define CXL_CAPABILITY_HEADER_OFFSET 0\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlCacheMemVersion : 4; // bit 20..23\r
- UINT32 ArraySize : 8; // bit 24..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlCacheMemVersion : 4; // bit 20..23\r
+ UINT32 ArraySize : 8; // bit 24..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CAPABILITY_HEADER;\r
\r
-#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4\r
+#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlRasCapabilityPointer : 12; // bit 20..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlRasCapabilityPointer : 12; // bit 20..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_RAS_CAPABILITY_HEADER;\r
\r
-#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8\r
+#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_SECURITY_CAPABILITY_HEADER;\r
\r
-#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC\r
+#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_LINK_CAPABILITY_HEADER;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataParity : 1; // bit 0..0\r
- UINT32 CacheAddressParity : 1; // bit 1..1\r
- UINT32 CacheByteEnableParity : 1; // bit 2..2\r
- UINT32 CacheDataEcc : 1; // bit 3..3\r
- UINT32 MemDataParity : 1; // bit 4..4\r
- UINT32 MemAddressParity : 1; // bit 5..5\r
- UINT32 MemByteEnableParity : 1; // bit 6..6\r
- UINT32 MemDataEcc : 1; // bit 7..7\r
- UINT32 ReInitThreshold : 1; // bit 8..8\r
- UINT32 RsvdEncodingViolation : 1; // bit 9..9\r
- UINT32 PoisonReceived : 1; // bit 10..10\r
- UINT32 ReceiverOverflow : 1; // bit 11..11\r
- UINT32 Reserved : 20; // bit 12..31\r
+ UINT32 CacheDataParity : 1; // bit 0..0\r
+ UINT32 CacheAddressParity : 1; // bit 1..1\r
+ UINT32 CacheByteEnableParity : 1; // bit 2..2\r
+ UINT32 CacheDataEcc : 1; // bit 3..3\r
+ UINT32 MemDataParity : 1; // bit 4..4\r
+ UINT32 MemAddressParity : 1; // bit 5..5\r
+ UINT32 MemByteEnableParity : 1; // bit 6..6\r
+ UINT32 MemDataEcc : 1; // bit 7..7\r
+ UINT32 ReInitThreshold : 1; // bit 8..8\r
+ UINT32 RsvdEncodingViolation : 1; // bit 9..9\r
+ UINT32 PoisonReceived : 1; // bit 10..10\r
+ UINT32 ReceiverOverflow : 1; // bit 11..11\r
+ UINT32 Reserved : 20; // bit 12..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataParityMask : 1; // bit 0..0\r
- UINT32 CacheAddressParityMask : 1; // bit 1..1\r
- UINT32 CacheByteEnableParityMask : 1; // bit 2..2\r
- UINT32 CacheDataEccMask : 1; // bit 3..3\r
- UINT32 MemDataParityMask : 1; // bit 4..4\r
- UINT32 MemAddressParityMask : 1; // bit 5..5\r
- UINT32 MemByteEnableParityMask : 1; // bit 6..6\r
- UINT32 MemDataEccMask : 1; // bit 7..7\r
- UINT32 ReInitThresholdMask : 1; // bit 8..8\r
- UINT32 RsvdEncodingViolationMask : 1; // bit 9..9\r
- UINT32 PoisonReceivedMask : 1; // bit 10..10\r
- UINT32 ReceiverOverflowMask : 1; // bit 11..11\r
- UINT32 Reserved : 20; // bit 12..31\r
+ UINT32 CacheDataParityMask : 1; // bit 0..0\r
+ UINT32 CacheAddressParityMask : 1; // bit 1..1\r
+ UINT32 CacheByteEnableParityMask : 1; // bit 2..2\r
+ UINT32 CacheDataEccMask : 1; // bit 3..3\r
+ UINT32 MemDataParityMask : 1; // bit 4..4\r
+ UINT32 MemAddressParityMask : 1; // bit 5..5\r
+ UINT32 MemByteEnableParityMask : 1; // bit 6..6\r
+ UINT32 MemDataEccMask : 1; // bit 7..7\r
+ UINT32 ReInitThresholdMask : 1; // bit 8..8\r
+ UINT32 RsvdEncodingViolationMask : 1; // bit 9..9\r
+ UINT32 PoisonReceivedMask : 1; // bit 10..10\r
+ UINT32 ReceiverOverflowMask : 1; // bit 11..11\r
+ UINT32 Reserved : 20; // bit 12..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_UNCORRECTABLE_ERROR_MASK;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataParitySeverity : 1; // bit 0..0\r
- UINT32 CacheAddressParitySeverity : 1; // bit 1..1\r
- UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2\r
- UINT32 CacheDataEccSeverity : 1; // bit 3..3\r
- UINT32 MemDataParitySeverity : 1; // bit 4..4\r
- UINT32 MemAddressParitySeverity : 1; // bit 5..5\r
- UINT32 MemByteEnableParitySeverity : 1; // bit 6..6\r
- UINT32 MemDataEccSeverity : 1; // bit 7..7\r
- UINT32 ReInitThresholdSeverity : 1; // bit 8..8\r
- UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9\r
- UINT32 PoisonReceivedSeverity : 1; // bit 10..10\r
- UINT32 ReceiverOverflowSeverity : 1; // bit 11..11\r
- UINT32 Reserved : 20; // bit 12..31\r
+ UINT32 CacheDataParitySeverity : 1; // bit 0..0\r
+ UINT32 CacheAddressParitySeverity : 1; // bit 1..1\r
+ UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2\r
+ UINT32 CacheDataEccSeverity : 1; // bit 3..3\r
+ UINT32 MemDataParitySeverity : 1; // bit 4..4\r
+ UINT32 MemAddressParitySeverity : 1; // bit 5..5\r
+ UINT32 MemByteEnableParitySeverity : 1; // bit 6..6\r
+ UINT32 MemDataEccSeverity : 1; // bit 7..7\r
+ UINT32 ReInitThresholdSeverity : 1; // bit 8..8\r
+ UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9\r
+ UINT32 PoisonReceivedSeverity : 1; // bit 10..10\r
+ UINT32 ReceiverOverflowSeverity : 1; // bit 11..11\r
+ UINT32 Reserved : 20; // bit 12..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataEcc : 1; // bit 0..0\r
- UINT32 MemoryDataEcc : 1; // bit 1..1\r
- UINT32 CrcThreshold : 1; // bit 2..2\r
- UINT32 RetryThreshold : 1; // bit 3..3\r
- UINT32 CachePoisonReceived : 1; // bit 4..4\r
- UINT32 MemoryPoisonReceived : 1; // bit 5..5\r
- UINT32 PhysicalLayerError : 1; // bit 6..6\r
- UINT32 Reserved : 25; // bit 7..31\r
+ UINT32 CacheDataEcc : 1; // bit 0..0\r
+ UINT32 MemoryDataEcc : 1; // bit 1..1\r
+ UINT32 CrcThreshold : 1; // bit 2..2\r
+ UINT32 RetryThreshold : 1; // bit 3..3\r
+ UINT32 CachePoisonReceived : 1; // bit 4..4\r
+ UINT32 MemoryPoisonReceived : 1; // bit 5..5\r
+ UINT32 PhysicalLayerError : 1; // bit 6..6\r
+ UINT32 Reserved : 25; // bit 7..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CORRECTABLE_ERROR_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataEccMask : 1; // bit 0..0\r
- UINT32 MemoryDataEccMask : 1; // bit 1..1\r
- UINT32 CrcThresholdMask : 1; // bit 2..2\r
- UINT32 RetryThresholdMask : 1; // bit 3..3\r
- UINT32 CachePoisonReceivedMask : 1; // bit 4..4\r
- UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5\r
- UINT32 PhysicalLayerErrorMask : 1; // bit 6..6\r
- UINT32 Reserved : 25; // bit 7..31\r
+ UINT32 CacheDataEccMask : 1; // bit 0..0\r
+ UINT32 MemoryDataEccMask : 1; // bit 1..1\r
+ UINT32 CrcThresholdMask : 1; // bit 2..2\r
+ UINT32 RetryThresholdMask : 1; // bit 3..3\r
+ UINT32 CachePoisonReceivedMask : 1; // bit 4..4\r
+ UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5\r
+ UINT32 PhysicalLayerErrorMask : 1; // bit 6..6\r
+ UINT32 Reserved : 25; // bit 7..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CORRECTABLE_ERROR_MASK;\r
\r
typedef union {\r
struct {\r
- UINT32 FirstErrorPointer : 4; // bit 0..3\r
- UINT32 Reserved1 : 5; // bit 4..8\r
- UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9\r
- UINT32 Reserved2 : 3; // bit 10..12\r
- UINT32 PoisonEnabled : 1; // bit 13..13\r
- UINT32 Reserved3 : 18; // bit 14..31\r
+ UINT32 FirstErrorPointer : 4; // bit 0..3\r
+ UINT32 Reserved1 : 5; // bit 4..8\r
+ UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9\r
+ UINT32 Reserved2 : 3; // bit 10..12\r
+ UINT32 PoisonEnabled : 1; // bit 13..13\r
+ UINT32 Reserved3 : 18; // bit 14..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_ERROR_CAPABILITIES_AND_CONTROL;\r
\r
typedef struct {\r
- CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;\r
- CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;\r
- CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;\r
- CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;\r
- CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;\r
- CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;\r
- UINT32 HeaderLog[16];\r
+ CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;\r
+ CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;\r
+ CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;\r
+ CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;\r
+ CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;\r
+ CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;\r
+ UINT32 HeaderLog[16];\r
} CXL_1_1_RAS_CAPABILITY_STRUCTURE;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus , 0x00);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask , 0x04);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity , 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus , 0x0C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus, 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask, 0x04);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity, 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus, 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask, 0x10);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog , 0x18);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog, 0x18);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, 0x58);\r
\r
typedef union {\r
struct {\r
- UINT32 DeviceTrustLevel : 2; // bit 0..1\r
- UINT32 Reserved : 30; // bit 2..31\r
+ UINT32 DeviceTrustLevel : 2; // bit 0..1\r
+ UINT32 Reserved : 30; // bit 2..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_SECURITY_POLICY;\r
\r
typedef struct {\r
- CXL_1_1_SECURITY_POLICY SecurityPolicy;\r
+ CXL_1_1_SECURITY_POLICY SecurityPolicy;\r
} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;\r
\r
CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);\r
\r
typedef union {\r
struct {\r
- UINT64 CxlLinkVersionSupported : 4; // bit 0..3\r
- UINT64 CxlLinkVersionReceived : 4; // bit 4..7\r
- UINT64 LlrWrapValueSupported : 8; // bit 8..15\r
- UINT64 LlrWrapValueReceived : 8; // bit 16..23\r
- UINT64 NumRetryReceived : 5; // bit 24..28\r
- UINT64 NumPhyReinitReceived : 5; // bit 29..33\r
- UINT64 WrPtrReceived : 8; // bit 34..41\r
- UINT64 EchoEseqReceived : 8; // bit 42..49\r
- UINT64 NumFreeBufReceived : 8; // bit 50..57\r
- UINT64 Reserved : 6; // bit 58..63\r
+ UINT64 CxlLinkVersionSupported : 4; // bit 0..3\r
+ UINT64 CxlLinkVersionReceived : 4; // bit 4..7\r
+ UINT64 LlrWrapValueSupported : 8; // bit 8..15\r
+ UINT64 LlrWrapValueReceived : 8; // bit 16..23\r
+ UINT64 NumRetryReceived : 5; // bit 24..28\r
+ UINT64 NumPhyReinitReceived : 5; // bit 29..33\r
+ UINT64 WrPtrReceived : 8; // bit 34..41\r
+ UINT64 EchoEseqReceived : 8; // bit 42..49\r
+ UINT64 NumFreeBufReceived : 8; // bit 50..57\r
+ UINT64 Reserved : 6; // bit 58..63\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 LlReset : 1; // bit 0..0\r
- UINT16 LlInitStall : 1; // bit 1..1\r
- UINT16 LlCrdStall : 1; // bit 2..2\r
- UINT16 InitState : 2; // bit 3..4\r
- UINT16 LlRetryBufferConsumed : 8; // bit 5..12\r
- UINT16 Reserved : 3; // bit 13..15\r
+ UINT16 LlReset : 1; // bit 0..0\r
+ UINT16 LlInitStall : 1; // bit 1..1\r
+ UINT16 LlCrdStall : 1; // bit 2..2\r
+ UINT16 InitState : 2; // bit 3..4\r
+ UINT16 LlRetryBufferConsumed : 8; // bit 5..12\r
+ UINT16 Reserved : 3; // bit 13..15\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_CONTROL_AND_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT64 CacheReqCredits : 10; // bit 0..9\r
- UINT64 CacheRspCredits : 10; // bit 10..19\r
- UINT64 CacheDataCredits : 10; // bit 20..29\r
- UINT64 MemReqRspCredits : 10; // bit 30..39\r
- UINT64 MemDataCredits : 10; // bit 40..49\r
+ UINT64 CacheReqCredits : 10; // bit 0..9\r
+ UINT64 CacheRspCredits : 10; // bit 10..19\r
+ UINT64 CacheDataCredits : 10; // bit 20..29\r
+ UINT64 MemReqRspCredits : 10; // bit 30..39\r
+ UINT64 MemDataCredits : 10; // bit 40..49\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_RX_CREDIT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT64 CacheReqCredits : 10; // bit 0..9\r
- UINT64 CacheRspCredits : 10; // bit 10..19\r
- UINT64 CacheDataCredits : 10; // bit 20..29\r
- UINT64 MemReqRspCredits : 10; // bit 30..39\r
- UINT64 MemDataCredits : 10; // bit 40..49\r
+ UINT64 CacheReqCredits : 10; // bit 0..9\r
+ UINT64 CacheRspCredits : 10; // bit 10..19\r
+ UINT64 CacheDataCredits : 10; // bit 20..29\r
+ UINT64 MemReqRspCredits : 10; // bit 30..39\r
+ UINT64 MemDataCredits : 10; // bit 40..49\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT64 CacheReqCredits : 10; // bit 0..9\r
- UINT64 CacheRspCredits : 10; // bit 10..19\r
- UINT64 CacheDataCredits : 10; // bit 20..29\r
- UINT64 MemReqRspCredits : 10; // bit 30..39\r
- UINT64 MemDataCredits : 10; // bit 40..49\r
+ UINT64 CacheReqCredits : 10; // bit 0..9\r
+ UINT64 CacheRspCredits : 10; // bit 10..19\r
+ UINT64 CacheDataCredits : 10; // bit 20..29\r
+ UINT64 MemReqRspCredits : 10; // bit 30..39\r
+ UINT64 MemDataCredits : 10; // bit 40..49\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_TX_CREDIT_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 AckForceThreshold : 8; // bit 0..7\r
- UINT32 AckFLushRetimer : 10; // bit 8..17\r
+ UINT32 AckForceThreshold : 8; // bit 0..7\r
+ UINT32 AckFLushRetimer : 10; // bit 8..17\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_ACK_TIMER_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT32 MdhDisable : 1; // bit 0..0\r
- UINT32 Reserved : 31; // bit 1..31\r
+ UINT32 MdhDisable : 1; // bit 0..0\r
+ UINT32 Reserved : 31; // bit 1..31\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_DEFEATURE;\r
\r
typedef struct {\r
- CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;\r
- CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;\r
- CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;\r
- CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;\r
- CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;\r
- CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;\r
- CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;\r
+ CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;\r
+ CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;\r
+ CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;\r
+ CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;\r
+ CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;\r
+ CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;\r
+ CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;\r
} CXL_1_1_LINK_CAPABILITY_STRUCTURE;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability , 0x00);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus , 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability, 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus, 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl, 0x10);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus , 0x20);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl , 0x28);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature , 0x30);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus, 0x20);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl, 0x28);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature, 0x30);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, 0x38);\r
\r
-#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180\r
+#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180\r
typedef union {\r
struct {\r
- UINT32 Reserved1 : 4; // bit 0..3\r
- UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
- UINT32 Reserved2 : 24; // bit 8..31\r
+ UINT32 Reserved1 : 4; // bit 0..3\r
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
+ UINT32 Reserved2 : 24; // bit 8..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_IO_ARBITRATION_CONTROL;\r
\r
CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);\r
\r
-#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0\r
+#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0\r
typedef union {\r
struct {\r
- UINT32 Reserved1 : 4; // bit 0..3\r
- UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
- UINT32 Reserved2 : 24; // bit 8..31\r
+ UINT32 Reserved1 : 4; // bit 0..3\r
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
+ UINT32 Reserved2 : 24; // bit 8..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;\r
\r
CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);\r
///@{\r
typedef union {\r
struct {\r
- UINT64 RcrbEnable : 1; // bit 0..0\r
- UINT64 Reserved : 12; // bit 1..12\r
- UINT64 RcrbBaseAddress : 51; // bit 13..63\r
+ UINT64 RcrbEnable : 1; // bit 0..0\r
+ UINT64 Reserved : 12; // bit 1..12\r
+ UINT64 RcrbBaseAddress : 51; // bit 13..63\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_RCRB_BASE;\r
\r
CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);\r
// CXL Downstream / Upstream Port RCRB space register offsets\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97\r
//\r
-#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010\r
-#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014\r
-#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100\r
+#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010\r
+#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014\r
+#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100\r
\r
#endif\r
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