- UINT8 ExtCsdRev; // Extended CSD revision [192]\r
- UINT8 Reserved14; // Reserved [193]\r
- UINT8 CsdStructure; // CSD STRUCTURE [194]\r
- UINT8 Reserved15; // Reserved [195]\r
- UINT8 DeviceType; // Device type [196]\r
- UINT8 DriverStrength; // I/O Driver Strength [197]\r
- UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]\r
- UINT8 PartitionSwitchTime; // Partition switching timing [199]\r
- UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]\r
- UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]\r
- UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]\r
- UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]\r
- UINT8 Reserved16; // Reserved [204]\r
- UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]\r
- UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]\r
- UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]\r
- UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]\r
- UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]\r
- UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]\r
- UINT8 Reserved17; // Reserved [211]\r
- UINT8 SecCount[4]; // Sector Count [215:212]\r
- UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]\r
- UINT8 SATimeout; // Sleep/awake timeout [217]\r
- UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]\r
- UINT8 SCVccq; // Sleep current (VCCQ) [219]\r
- UINT8 SCVcc; // Sleep current (VCC) [220]\r
- UINT8 HcWpGrpSize; // High-capacity write protect group size [221]\r
- UINT8 RelWrSecC; // Reliable write sector count [222]\r
- UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]\r
- UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]\r
- UINT8 AccSize; // Access size [225]\r
- UINT8 BootSizeMult; // Boot partition size [226]\r
- UINT8 Reserved18; // Reserved [227]\r
- UINT8 BootInfo; // Boot information [228]\r
- UINT8 SecTrimMult; // Secure TRIM Multiplier [229]\r
- UINT8 SecEraseMult; // Secure Erase Multiplier [230]\r
- UINT8 SecFeatureSupport; // Secure Feature support [231]\r
- UINT8 TrimMult; // TRIM Multiplier [232]\r
- UINT8 Reserved19; // Reserved [233]\r
- UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]\r
- UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]\r
- UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]\r
- UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]\r
- UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]\r
- UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]\r
- UINT8 Reserved20; // Reserved [240]\r
- UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]\r
- UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]\r
- UINT8 BkopsStatus; // Background operations status [246]\r
- UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]\r
- UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]\r
- UINT8 CacheSize[4]; // Cache size [252:249]\r
- UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]\r
- UINT8 FirmwareVersion[8]; // Firmware version [261:254]\r
- UINT8 DeviceVersion[2]; // Device version [263:262]\r
- UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]\r
- UINT8 OptimalWriteSize; // Optimal write size [265]\r
- UINT8 OptimalReadSize; // Optimal read size [266]\r
- UINT8 PreEolInfo; // Pre EOL information [267]\r
- UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]\r
- UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]\r
- UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]\r
- UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]\r
- UINT8 Reserved21[181]; // Reserved [486:306]\r
- UINT8 FfuArg[4]; // FFU Argument [490:487]\r
- UINT8 OperationCodeTimeout; // Operation codes timeout [491]\r
- UINT8 FfuFeatures; // FFU features [492]\r
- UINT8 SupportedModes; // Supported modes [493]\r
- UINT8 ExtSupport; // Extended partitions attribute support [494]\r
- UINT8 LargeUnitSizeM1; // Large Unit size [495]\r
- UINT8 ContextCapabilities; // Context management capabilities [496]\r
- UINT8 TagResSize; // Tag Resources Size [497]\r
- UINT8 TagUnitSize; // Tag Unit Size [498]\r
- UINT8 DataTagSupport; // Data Tag Support [499]\r
- UINT8 MaxPackedWrites; // Max packed write commands [500]\r
- UINT8 MaxPackedReads; // Max packed read commands[501]\r
- UINT8 BkOpsSupport; // Background operations support [502]\r
- UINT8 HpiFeatures; // HPI features [503]\r
- UINT8 SupportedCmdSet; // Supported Command Sets [504]\r
- UINT8 ExtSecurityErr; // Extended Security Commands Error [505]\r
- UINT8 Reserved22[6]; // Reserved [511:506]\r
+ UINT8 ExtCsdRev; // Extended CSD revision [192]\r
+ UINT8 Reserved14; // Reserved [193]\r
+ UINT8 CsdStructure; // CSD STRUCTURE [194]\r
+ UINT8 Reserved15; // Reserved [195]\r
+ UINT8 DeviceType; // Device type [196]\r
+ UINT8 DriverStrength; // I/O Driver Strength [197]\r
+ UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]\r
+ UINT8 PartitionSwitchTime; // Partition switching timing [199]\r
+ UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]\r
+ UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]\r
+ UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]\r
+ UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]\r
+ UINT8 Reserved16; // Reserved [204]\r
+ UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]\r
+ UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]\r
+ UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]\r
+ UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]\r
+ UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]\r
+ UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]\r
+ UINT8 Reserved17; // Reserved [211]\r
+ UINT8 SecCount[4]; // Sector Count [215:212]\r
+ UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]\r
+ UINT8 SATimeout; // Sleep/awake timeout [217]\r
+ UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]\r
+ UINT8 SCVccq; // Sleep current (VCCQ) [219]\r
+ UINT8 SCVcc; // Sleep current (VCC) [220]\r
+ UINT8 HcWpGrpSize; // High-capacity write protect group size [221]\r
+ UINT8 RelWrSecC; // Reliable write sector count [222]\r
+ UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]\r
+ UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]\r
+ UINT8 AccSize; // Access size [225]\r
+ UINT8 BootSizeMult; // Boot partition size [226]\r
+ UINT8 Reserved18; // Reserved [227]\r
+ UINT8 BootInfo; // Boot information [228]\r
+ UINT8 SecTrimMult; // Secure TRIM Multiplier [229]\r
+ UINT8 SecEraseMult; // Secure Erase Multiplier [230]\r
+ UINT8 SecFeatureSupport; // Secure Feature support [231]\r
+ UINT8 TrimMult; // TRIM Multiplier [232]\r
+ UINT8 Reserved19; // Reserved [233]\r
+ UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]\r
+ UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]\r
+ UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]\r
+ UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]\r
+ UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]\r
+ UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]\r
+ UINT8 Reserved20; // Reserved [240]\r
+ UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]\r
+ UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]\r
+ UINT8 BkopsStatus; // Background operations status [246]\r
+ UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]\r
+ UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]\r
+ UINT8 CacheSize[4]; // Cache size [252:249]\r
+ UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]\r
+ UINT8 FirmwareVersion[8]; // Firmware version [261:254]\r
+ UINT8 DeviceVersion[2]; // Device version [263:262]\r
+ UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]\r
+ UINT8 OptimalWriteSize; // Optimal write size [265]\r
+ UINT8 OptimalReadSize; // Optimal read size [266]\r
+ UINT8 PreEolInfo; // Pre EOL information [267]\r
+ UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]\r
+ UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]\r
+ UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]\r
+ UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]\r
+ UINT8 Reserved21[181]; // Reserved [486:306]\r
+ UINT8 FfuArg[4]; // FFU Argument [490:487]\r
+ UINT8 OperationCodeTimeout; // Operation codes timeout [491]\r
+ UINT8 FfuFeatures; // FFU features [492]\r
+ UINT8 SupportedModes; // Supported modes [493]\r
+ UINT8 ExtSupport; // Extended partitions attribute support [494]\r
+ UINT8 LargeUnitSizeM1; // Large Unit size [495]\r
+ UINT8 ContextCapabilities; // Context management capabilities [496]\r
+ UINT8 TagResSize; // Tag Resources Size [497]\r
+ UINT8 TagUnitSize; // Tag Unit Size [498]\r
+ UINT8 DataTagSupport; // Data Tag Support [499]\r
+ UINT8 MaxPackedWrites; // Max packed write commands [500]\r
+ UINT8 MaxPackedReads; // Max packed read commands[501]\r
+ UINT8 BkOpsSupport; // Background operations support [502]\r
+ UINT8 HpiFeatures; // HPI features [503]\r
+ UINT8 SupportedCmdSet; // Supported Command Sets [504]\r
+ UINT8 ExtSecurityErr; // Extended Security Commands Error [505]\r
+ UINT8 Reserved22[6]; // Reserved [511:506]\r